利索-全球专利检索

  1. 登录
  2. 注册

搜索结果

126 条记录 (耗时 0.049 秒)

    Method and apparatus for synchronized pipeline data access of a memory system
    1.
    发明授权
    Method and apparatus for synchronized pipeline data access of a memory system 失效
    用于存储器系统的同步流水线数据访问的方法和装置

    公开(公告)号：US5615168A

    公开(公告)日：1997-03-25

    申请号：US538085

    申请日：1995-10-02

    申请人： George M. Lattimore ,  Michael K. Ciraula ,  Manoj Kumar ,  Joseph M. Poplawski, Jr. ,  Dieter F. Wendel ,  Friedrich Wernicke

    发明人： George M. Lattimore ,  Michael K. Ciraula ,  Manoj Kumar ,  Joseph M. Poplawski, Jr. ,  Dieter F. Wendel ,  Friedrich Wernicke

    IPC分类号： G11C7/10 ,  G11C7/00

    CPC分类号： G11C7/1072

    摘要： A method and apparatus for providing single clock cycle pipelined access of a memory system, which combines synchronization and self resetting techniques, includes an array of memory cells that are arranged into columns and rows and intercoupled by bit lines and word lines. The memory system also includes an address decoder and a sense enable circuit. The address decoder, upon receiving an address, interprets the address to enable a particular word line, or word lines, and to disable precharging of a bit line, or bit lines. With the word line active, the sense enable circuit generates a sense enable signal when the clock signal has encountered a transitional edge, or is in an active state. When the sense enable signal is active, the sense amplifier reads the data from the addressed memory cell via the bit lines to produce output data.

    摘要翻译： 用于提供组合同步和自复位技术的存储器系统的单时钟周期流水线访问的方法和装置包括排列成列和行并由位线和字线相互配合的存储器单元阵列。 存储器系统还包括地址解码器和感测使能电路。 地址解码器在接收到地址后，解释地址以启用特定字线或字线，并禁止位线或位线的预充电。 当字线有效时，当时钟信号遇到过渡沿或处于活动状态时，感测使能电路产生检测使能信号。 当感测使能信号有效时，读出放大器通过位线从寻址的存储单元读取数据，以产生输出数据。

    Reset generation circuit to reset self resetting CMOS circuits
    2.
    发明授权
    Reset generation circuit to reset self resetting CMOS circuits 失效
    复位发生电路以复位自复位CMOS电路

    公开(公告)号：US5467037A

    公开(公告)日：1995-11-14

    申请号：US342967

    申请日：1994-11-21

    申请人： Manoj Kumar ,  George M. Lattimore ,  Joseph M. Poplawski, Jr.

    发明人： Manoj Kumar ,  George M. Lattimore ,  Joseph M. Poplawski, Jr.

    IPC分类号： H03K3/356 ,  H03L7/00

    CPC分类号： H03K3/356008

    摘要： A self resetting CMOS (SRCMOS) circuit operates with a variable clock cycle. Circuit oscillation is avoided in either long or short clock cycles. At the same time, the circuit eliminates overlapping currents by incorporating a ground interrupt device. The reset generation path is optimized to provide a fast and narrow reset pulse. In addition, the circuit saves power.

    摘要翻译： 自复位CMOS（SRCMOS）电路以可变的时钟周期工作。 在长或短时钟周期内避免电路振荡。 同时，该电路通过并入接地中断装置来消除重叠电流。 复位产生路径被优化以提供快速和窄的复位脉冲。 此外，电路节省电力。

    Word line driver circuit
    3.
    发明授权
    Word line driver circuit 失效
    字线驱动电路

    公开(公告)号：US5544112A

    公开(公告)日：1996-08-06

    申请号：US457704

    申请日：1995-06-02

    申请人： Manoj Kumar ,  Joseph M. Poplawski, Jr.

    发明人： Manoj Kumar ,  Joseph M. Poplawski, Jr.

    IPC分类号： G11C11/413 ,  G11C8/08 ,  G11C11/407 ,  G11C8/00 ,  H03K19/017

    CPC分类号： G11C8/08

    摘要： A word line driver circuit operable for receiving address signals from a decoder circuit and for gating these address signals to be outputted as a word line signal to one or more memory cells within a RAM. The driver circuit prevents oscillations of the outputted word line signal by not allowing any internal nodes between circuit elements to have a floating potential. This function is provided by a plurality of circuit elements arranged in a unique manner so that the internal nodes are not allowed to float.

    摘要翻译： 字线驱动器电路，用于从解码器电路接收地址信号，并将这些地址信号选通作为字线信号输出到RAM内的一个或多个存储器单元。 驱动器电路通过不允许电路元件之间的任何内部节点具有浮动电位来防止输出的字线信号的振荡。 该功能由以独特方式布置的多个电路元件提供，使得内部节点不被允许浮动。

    System and method for testing self-timed memory arrays
    4.
    发明授权
    System and method for testing self-timed memory arrays 失效
    用于测试自定时存储器阵列的系统和方法

    公开(公告)号：US5896399A

    公开(公告)日：1999-04-20

    申请号：US763493

    申请日：1996-12-11

    申请人： George McNeil Lattimore ,  Michael Kevin Ciraula ,  Dieter F. Wendel ,  Manoj Kumar ,  Friedrich-Christian Wernicke

    发明人： George McNeil Lattimore ,  Michael Kevin Ciraula ,  Dieter F. Wendel ,  Manoj Kumar ,  Friedrich-Christian Wernicke

    IPC分类号： G11C29/14 ,  G11C29/00

    CPC分类号： G11C29/14

    摘要： The present invention applies a Static Evaluate technique to a memory array in a selective manner that allows some parts of the array to use the technique, and yet keeps the array area and timing unaffected for normal operation. The present invention allows the decode functions of the memory array to become pseudo-static during a first part of a clock cycle. In addition, if a write function is being performed, the write data is also held pseudo-static and is not written until a second part of a clock cycle when all addresses and data have stabilized. The invention can be used for system debug, product bring-up, or burn-in, even if there are non-functional race paths. A system and method of testing and burning in self-timed memory arrays includes a Static Evaluate circuit applied to the decoding function and the writing function of the array, a circuit for holding an address or write data inactive for the first part of a cycle, a circuit for activating the address or write data for the second part of a cycle, and a circuit for ensuring that the array resets correctly.

    摘要翻译： 本发明以选择性方式将静态评估技术应用于存储器阵列，其允许阵列的某些部分使用该技术，并且仍保持阵列区域和定时不受正常操作的影响。 本发明允许存储器阵列的解码功能在时钟周期的第一部分期间变为伪静态。 此外，如果正在执行写入功能，则写入数据也保持为伪静态，并且在所有地址和数据均已稳定时，不会写入时钟周期的第二部分。 即使存在非功能性赛跑路径，本发明也可用于系统调试，产品开机或老化。 在自定时存储器阵列中测试和刻录的系统和方法包括应用于解码功能的静态评估电路和阵列的写入功能，用于保持地址或写入对于循环的第一部分无效的数据的电路， 用于激活用于周期的第二部分的地址或写入数据的电路，以及用于确保阵列正确复位的电路。

    Polyol oxidases
    10.
    发明授权
    Polyol oxidases 有权
    多元氧化酶

    公开(公告)号：US07919295B2

    公开(公告)日：2011-04-05

    申请号：US11875788

    申请日：2007-10-19

    申请人： Manoj Kumar ,  Susan M. Madrid ,  Hugh C. McDonald ,  Ayrookaran J. Poulose ,  Thomas Rand ,  Huaming Wang

    发明人： Manoj Kumar ,  Susan M. Madrid ,  Hugh C. McDonald ,  Ayrookaran J. Poulose ,  Thomas Rand ,  Huaming Wang

    IPC分类号： C12N9/00 ,  C12N9/02 ,  C12N1/20 ,  C12N15/00 ,  C07H21/04

    CPC分类号： C12N9/0006 ,  C07K2319/02 ,  C11D3/38654 ,  C12Y101/03

    摘要： The present invention provides compositions and methods for producing a polyol oxidase in microorganisms, and the use of polyol oxidases in cleaning compositions. The invention includes cleaning compositions that contain combinations of two or more POx oxidases, and cleaning compositions that contain combinations of two or more POx oxidases and a perhydrolase. In particular, the invention provides methods for expressing polyol oxidases in bacterial hosts for use in detergent applications for cleaning, bleaching and disinfecting.

    摘要翻译： 本发明提供了用于在微生物中生产多元醇氧化酶的组合物和方法，以及在清洁组合物中使用多元醇氧化酶。 本发明包括含有两种或更多种POx氧化酶的组合的清洁组合物和含有两种或更多种POx氧化酶和过水解酶的组合的清洁组合物。 特别地，本发明提供了用于在洗涤剂应用中用于清洁，漂白和消毒的细菌宿主中表达多元氧化酶的方法。