公开(公告)号：US07576758B2

公开(公告)日：2009-08-18

申请号：US11370533

申请日：2006-03-08

申请人： Sreenivas Kothandaraman ,  Joseph R. Zbiciak

发明人： Sreenivas Kothandaraman ,  Joseph R. Zbiciak

IPC分类号： G09G5/00

CPC分类号： G06T3/606

摘要： Rotation in the storage domain is a one-one function with the domain equal to the range. This permits an image to be rotated in place. Each image size implies at least one garland of closed chains of tiles. Each image includes a spanning set of these garlands. Rotation in place moves each pixel to the next location on its garland. On completion of a garland by return to the initial tile, tiles on the next garland are moved. Image rotation is complete after all the garlands have been traversed. This invention first linearized the two-dimensional tiles sliding into groups of super-pixels at contiguous locations above the image buffer. The tiles are rotated in place. The shuffled tiles are delinearized into rectangular blocks and then re-pitched if needed.

摘要翻译： 存储域中的旋转是一个单一函数，其域等于该范围。 这允许图像旋转到位。 每个图像大小意味着至少一个封闭的瓦片链的花环。 每个图像包括这些花环的跨越。 旋转到位将每个像素移动到其花环上的下一个位置。 通过返回初始瓷砖完成花环，下一个花环上的瓷砖被移动。 所有花环遍历后，图像旋转完成。 本发明首先将二维瓦片线性化成在图像缓冲器上方的连续位置滑动成超像素组。 瓦片旋转到位。 洗牌砖被划分成矩形块，然后如果需要重新调整。

公开(公告)号：US08112652B2

公开(公告)日：2012-02-07

申请号：US12356274

申请日：2009-01-20

申请人： Sajish Sajayan ,  Alok Anand ,  Sudhakar Surendran ,  Ashish Rai Shrivastava ,  Joseph R. Zbiciak

发明人： Sajish Sajayan ,  Alok Anand ,  Sudhakar Surendran ,  Ashish Rai Shrivastava ,  Joseph R. Zbiciak

IPC分类号： G06F1/32

CPC分类号： G06F12/0862 ,  G06F13/16 ,  G06F2212/1032 ,  Y02D10/13 ,  Y02D10/14

摘要： This invention manages power down and wakeup of shared memories in a multiprocessor system. A register for each shared memory has bits corresponding to each master. When a master wants to power down a memory, it sets its corresponding bit in the register. A hardware power down controller for the memory bank powers the memory bank if any processor signals powering the memory bank. The hardware power down controller for the memory bank powers down the memory bank only if all processor signal powering down the memory bank. The hardware power down controller waits for all masters to set their corresponding bits in the register before initiating power down of the memories. Software running on any processor has a view of the shared memory independent of the other processors and no inter-processor communication is needed.

摘要翻译： 本发明管理多处理器系统中的共享存储器的掉电和唤醒。 每个共享存储器的寄存器具有与每个主器件相对应的位。 当主机要关闭存储器时，它将其相应的位置于寄存器中。 如果任何处理器信号为存储体供电，则存储器组件的硬件掉电控制器为存储体供电。 存储器的硬件​​掉电控制器只有在所有处理器信号使存储器电源断电的情况下才能关闭存储器。 在启动存储器掉电之前，硬件掉电控制器等待所有主器件在寄存器中设置相应的位。 在任何处理器上运行的软件具有独立于其他处理器的共享存储器的视图，并且不需要处理器间通信。

公开(公告)号：US07315261B2

公开(公告)日：2008-01-01

申请号：US10884461

申请日：2004-07-02

申请人： Joseph R. Zbiciak

发明人： Joseph R. Zbiciak

IPC分类号： H03M7/00

CPC分类号： G06F9/30032 ,  G06F9/30018 ,  G06F9/30036

摘要： This invention efficiently converts normal pixel data into bit plane data. A sequence of pack, bitwise shuffle, masking, rotate and merging operations transform tile from pixel form to bit plane form. This enables downstream algorithms to read only the data for the bit plane of interest. This greatly reduces the memory bandwidth bottleneck and opens many new optimization pathways.

摘要翻译： 本发明有效地将普通像素数据转换成位平面数据。 打包，按位洗牌，屏蔽，旋转和合并操作的顺序将图块从像素形式转换为位平面形式。 这使得下游算法只能读取感兴趣的位平面的数据。 这大大降低了内存带宽瓶颈，并开辟了许多新的优化路径。

公开(公告)号：US08627032B2

公开(公告)日：2014-01-07

申请号：US13204002

申请日：2011-08-05

申请人： Joseph R. Zbiciak

发明人： Joseph R. Zbiciak

IPC分类号： G06F12/14

CPC分类号： G06F12/1483 ,  G06F12/14 ,  G06F12/1425 ,  G06F12/1433 ,  G06F12/1441 ,  G06F12/1458 ,  G06F12/1491 ,  G06F13/366 ,  G06F21/78 ,  G06F21/79 ,  G06F2212/1052 ,  Y02D10/14

摘要： A memory management and protection system that manages memory access requests from a number of requestors. Memory accesses are allowed or disallowed based on the permissions assigned to the request based on the memory segment being accessed. The decision to allow or disallow access is made by the extended memory controller by merging the permissions assigned to the memory segment being accessed, and the permissions assigned to the access request by the originating memory controller or other endpoint.

摘要翻译： 一种管理来自多个请求者的存储器访问请求的存储器管理和保护系统。 基于正在访问的存储器段，基于分配给请求的许可，允许或不允许存储器访问。 扩展内存控制器通过合并分配给正在访问的内存段的权限以及由始发内存控制器或其他端点分配给访问请求的权限，来决定是否允许访问。

公开(公告)号：US20090248991A1

公开(公告)日：2009-10-01

申请号：US12356303

申请日：2009-01-20

申请人： Sajish Sajayan ,  Alok Anand ,  Ashish Rai Shrivastava ,  Joseph R. Zbiciak

发明人： Sajish Sajayan ,  Alok Anand ,  Ashish Rai Shrivastava ,  Joseph R. Zbiciak

IPC分类号： G06F12/00

CPC分类号： G06F12/0862 ,  G06F13/16 ,  G06F2212/1032 ,  Y02D10/13 ,  Y02D10/14

摘要： A real request from a CPU to the same memory bank as a prior prefetch request is transmitted to the per-memory bank logic along with a kill signal to terminate the prefetch request. This avoids waiting for a prefetch request to complete before sending the real request to the same memory bank. The kill signal gates off any acknowledgement of completion of the prefetch request. This invention reduces the latency for completion of a high priority real request when a low priority speculative request to a different address in the same memory bank has already been dispatched.

摘要翻译： 与先前的预取请求相关联的来自CPU到同一存储体的实际请求将与杀死信号一起发送到每存储器存储体逻辑以终止预取请求。 这避免了在将实际请求发送到同一个存储体之前等待预取请求完成。 杀死信号禁止任何完成预取请求的确认。 当对同一存储体中的不同地址的低优先级推测请求已经被分派时，本发明减少了完成高优先级实际请求的等待时间。

公开(公告)号：US08301928B2

公开(公告)日：2012-10-30

申请号：US12356294

申请日：2009-01-20

申请人： Sajish Sajayan ,  Alok Anand ,  Joseph R. Zbiciak

发明人： Sajish Sajayan ,  Alok Anand ,  Joseph R. Zbiciak

IPC分类号： G06F1/00

CPC分类号： G06F12/0862 ,  G06F13/16 ,  G06F2212/1032 ,  Y02D10/13 ,  Y02D10/14

摘要： A hardware based wake-up scheme initiates memory power-up upon a normal access to a powered down memory. The access that triggered the power-up is buffered. Further accesses are stalled until the memory is completely powered up. The buffered access then proceeds to the memory and the processor is brought out of stall. In cases where the software does not directly control access to the memory, such as on a cache miss, this scheme avoids undesirable conditions due to access to powered down memories.

摘要翻译： 基于硬件的唤醒方案在正常访问掉电存储器时启动内存上电。 触发上电的访问被缓冲。 进一步的访问停止，直到内存完全通电。 然后，缓冲的访问进行到存储器，并且处理器被摆脱失速。 在软件不直接控制访问存储器（例如高速缓存未命中）的情况下，该方案避免了由于访问掉电存储器而导致的不期望的状况。

公开(公告)号：US20120272027A1

公开(公告)日：2012-10-25

申请号：US13204002

申请日：2011-08-05

申请人： Joseph R. Zbiciak

发明人： Joseph R. Zbiciak

IPC分类号： G06F12/14

CPC分类号： G06F12/1483 ,  G06F12/14 ,  G06F12/1425 ,  G06F12/1433 ,  G06F12/1441 ,  G06F12/1458 ,  G06F12/1491 ,  G06F13/366 ,  G06F21/78 ,  G06F21/79 ,  G06F2212/1052 ,  Y02D10/14

摘要： A memory management and protection system that manages memory access requests from a number of requestors. Memory accesses are allowed or disallowed based on the permissions assigned to the request based on the memory segment being accessed. The decision to allow or disallow access is made by the extended memory controller by merging the permissions assigned to the memory segment being accessed, and the permissions assigned to the access request by the originating memory controller or other endpoint.

摘要翻译： 一种管理来自多个请求者的存储器访问请求的存储器管理和保护系统。 基于正在访问的存储器段，基于分配给请求的许可，允许或不允许存储器访问。 扩展内存控制器通过合并分配给正在访问的内存段的权限以及由始发内存控制器或其他端点分配给访问请求的权限，来决定是否允许访问。

公开(公告)号：US07890566B1

公开(公告)日：2011-02-15

申请号：US09703034

申请日：2000-10-31

申请人： Joseph R. Zbiciak

发明人： Joseph R. Zbiciak

IPC分类号： G06F7/38

CPC分类号： G06F9/30014 ,  G06F7/49963 ,  G06F7/5443

摘要： A functional unit in a digital system is provided with a rounding DOT product instruction, wherein a product of first pair of elements is combined with a product of second pair of elements, the combined product is rounded, and the final result is stored in a destination. Rounding is performed by adding a rounding value to form an intermediate result, and then shifting the intermediate result right. A combined result is rounded to a fixed length shorter than the combined product. The products are combined by either addition or subtraction. An overflow resulting from the combination or from rounding is not reported.

摘要翻译： 数字系统中的功能单元具有舍入DOT产品指令，其中第一对元件的乘积与第二对元件的乘积组合，组合产品被舍入，最终结果存储在目的地 。 通过添加舍入值以形成中间结果来执行舍入，然后将中间结果右移。 组合的结果被舍入到比组合产品短的固定长度。 产品通过加法或减法组合。 没有报告由组合或四舍五入引起的溢出。

公开(公告)号：US06757819B1

公开(公告)日：2004-06-29

申请号：US09703141

申请日：2000-10-31

申请人： David Hoyle ,  Richard H. Scales ,  Min Wang ,  Joseph R. Zbiciak

发明人： David Hoyle ,  Richard H. Scales ,  Min Wang ,  Joseph R. Zbiciak

IPC分类号： G06F1582

CPC分类号： G06F9/30032 ,  G06F9/30072

摘要： A data processing system is provided with a digital signal processor which has an instruction for shifting a source operand in response to a signed shift count value and storing the shifted result in a selected destination register. A first 32-bit operand (600) is treated as a signed shift value that has a sign and a shift count value. A second operand (602) is shifted by an amount according to the shift count value and in a direction according to the sign of the shift count. One instruction is provided that performs a right shift for a positive shift count and a left shift for a negative shift count, and another instruction is provided performs a left shift for a positive shift count and a right shift for a negative shift count. If the shift count value is greater than 31, then the shift is limited to 31.

摘要翻译： 数据处理系统具有数字信号处理器，该数字信号处理器具有响应于有符号移位计数值移位源操作数并将移位结果存储在所选择的目标寄存器中的指令。 第一个32位操作数（600）被视为具有符号和移位计数值的有符号位移值。 第二操作数（602）根据移位计数值和根据移位计数的符号的方向移位量。 提供一个指令，其执行用于正移位计数的右移位和用于负移位计数的左移位，并且提供另一指令来执行用于正移位计数的左移位和负移位计数的右移位。 如果移位计数值大于31，则移位限制为31。

公开(公告)号：US06560288B1

公开(公告)日：2003-05-06

申请号：US09464732

申请日：1999-12-15

申请人： Marcus Alan Gilbert ,  Joseph R. Zbiciak

发明人： Marcus Alan Gilbert ,  Joseph R. Zbiciak

IPC分类号： H04N712

CPC分类号： H03M7/40 ,  H03M7/42 ,  H04N19/61 ,  H04N19/91

摘要： Variable length codes in a compressed data stream are identified by determining a leading position of a specified value in the compressed data stream. A length of a leading code in the compressed data stream is then determined based on the leading position of the specified value.

摘要翻译： 通过确定压缩数据流中的指定值的前导位置来识别压缩数据流中的可变长度代码。 然后基于指定值的前导位置确定压缩数据流中的前导码的长度。