公开(公告)号：US20050064661A1

公开(公告)日：2005-03-24

申请号：US10874579

申请日：2004-06-24

申请人： Yong-Sun Lee ,  Jae-Min Yu ,  Don-Woo Lee ,  Jung-Hun Cho ,  Chul-Soon Kwon ,  Jung-Ho Moon ,  In-Gu Yoon ,  Jae-Hyun Park

发明人： Yong-Sun Lee ,  Jae-Min Yu ,  Don-Woo Lee ,  Jung-Hun Cho ,  Chul-Soon Kwon ,  Jung-Ho Moon ,  In-Gu Yoon ,  Jae-Hyun Park

IPC分类号： H01L21/8247 ,  H01L21/28 ,  H01L21/336 ,  H01L27/115 ,  H01L29/423 ,  H01L29/788 ,  H01L29/792

CPC分类号： H01L29/66825 ,  H01L21/28273 ,  H01L29/42324

摘要： A method of fabricating a flash memory cell having a split gate structure. A sacrificial layer is formed on a floating gate layer formed on a semiconductor substrate. The sacrificial layer is etched to form an opening exposing a portion of the floating gate layer. A gate interlayer insulating layer pattern is formed inside the opening. After removing the sacrificial layer pattern and etching the floating gate layer (using the gate interlayer insulating layer pattern as an etch mask), a floating gate is formed under the gate interlayer insulating layer pattern. A control gate is formed overlapping a portion of the floating gate.

摘要翻译： 一种制造具有分裂栅极结构的闪存单元的方法。 牺牲层形成在形成在半导体衬底上的浮栅上。 牺牲层被蚀刻以形成暴露浮动栅极层的一部分的开口。 在开口内部形成栅极层间绝缘层图案。 在去除牺牲层图案并蚀刻浮栅（使用栅极层间绝缘层图案作为蚀刻掩模）之后，在栅极层间绝缘层图案下方形成浮栅。 控制栅极形成为与浮置栅极的一部分重叠。

公开(公告)号：US20080095953A1

公开(公告)日：2008-04-24

申请号：US11923395

申请日：2007-10-24

申请人： Heok-Jae LEE ,  Jung-Hun CHO ,  Se-Hwi CHO ,  Yun-Sik YANG ,  Yong-Gyu LIM

发明人： Heok-Jae LEE ,  Jung-Hun CHO ,  Se-Hwi CHO ,  Yun-Sik YANG ,  Yong-Gyu LIM

IPC分类号： C23C16/00 ,  H05H1/24

CPC分类号： H01J37/3244 ,  C23C16/45578

摘要： Provided are an apparatus for depositing a thin film using plasma which can prevent impurities from being formed by inhibiting plasma from being diffused into a nozzle pipe and sustained in the nozzle pipe and improve thickness uniformity of the deposited thin film and a method of depositing the same. The apparatus for depositing a thin film includes a chamber having a substrate holder and an inner space defined by an inner wall; and a nozzle pipe comprising a first end fixed to the inner wall of the chamber; a second end extending into the inner space of the chamber; a flow path penetrating the nozzle pipe from the first end to the second end; and at least one slit which is disposed at the second end and opens the flow path into the inner space of the chamber.

摘要翻译： 提供了一种使用等离子体沉积薄膜的装置，其可以通过抑制等离子体扩散到喷嘴管中并保持在喷嘴管中并且改善沉积的薄膜的厚度均匀性来防止杂质形成和沉积薄膜的方法 。 用于沉积薄膜的装置包括具有衬底保持器和由内壁限定的内部空间的腔室; 以及喷嘴管，其包括固定到所述室的内壁的第一端; 延伸到所述室的内部空间中的第二端; 从所述第一端到所述第二端穿过所述喷嘴管的流路; 以及至少一个狭缝，其设置在所述第二端并且打开到所述室的内部空间的流动路径。

公开(公告)号：US20060278341A1

公开(公告)日：2006-12-14

申请号：US11506833

申请日：2006-08-21

申请人： Jeong-hyuck Park ,  Hee-duk Kim ,  Jung-hun Cho ,  Jong-wook Choi ,  Sung-bum Cho ,  Young-koo Lee ,  Jin-sung Kim ,  Jang-eun Lee ,  Ju-hyuck Chung ,  Sun-hoo Park ,  Jae-hyun Lee ,  Shin-woo Nam

发明人： Jeong-hyuck Park ,  Hee-duk Kim ,  Jung-hun Cho ,  Jong-wook Choi ,  Sung-bum Cho ,  Young-koo Lee ,  Jin-sung Kim ,  Jang-eun Lee ,  Ju-hyuck Chung ,  Sun-hoo Park ,  Jae-hyun Lee ,  Shin-woo Nam

IPC分类号： H01L21/306

CPC分类号： H01J37/32431 ,  C23C16/4583 ,  C23C16/4585 ,  C23C16/54 ,  H01J37/32623 ,  H01J37/32642 ,  H01L21/32136 ,  H01L21/6831 ,  H01L21/68735 ,  Y10T117/10

摘要： A process chamber used in the manufacture of a semiconductor device for etching a material layer on a semiconductor wafer includes an electrostatic chuck for holding the semiconductor wafer, and an annular edge ring which surrounds the side of the semiconductor wafer on the electrostatic chuck to prevent the semiconductor wafer from departing from its original position. The annular edge ring has a first side which faces the side of the semiconductor wafer and contacts firmly with the side of the semiconductor wafer.

公开(公告)号：US20050022742A1

公开(公告)日：2005-02-03

申请号：US10900150

申请日：2004-07-28

申请人： Hyung-Sik Hong ,  Gyeong-Su Keum ,  Yong-Gab Kim ,  Chung-Hun Park ,  Do-In Bae ,  Seung-Ki Chae ,  Jung-Hun Cho

发明人： Hyung-Sik Hong ,  Gyeong-Su Keum ,  Yong-Gab Kim ,  Chung-Hun Park ,  Do-In Bae ,  Seung-Ki Chae ,  Jung-Hun Cho

IPC分类号： H01L21/205 ,  C23C16/458 ,  H01L21/00 ,  C23C16/00

CPC分类号： H01L21/67103 ,  C23C16/4586

摘要： Chemical vapor deposition (CVD) processing equipment for use in fabricating a semiconductor device requiring deposition of an insulation layer or a metal layer includes a chamber having an exhaust line in a lower central portion thereof, a heater block for supporting a wafer to be supplied in an interior of the chamber, the heater block having a heating plate in an interior thereof, a support shaft for supporting the heater block, and an electrical wire for providing an electrical connection to the heating plate. The support shaft extends through a bottom of the chamber. The electrical wire extends through the bottom of the chamber within the support shaft.

摘要翻译： 用于制造需要沉积绝缘层或金属层的半导体器件的化学气相沉积（CVD）处理设备包括在其下部中心具有排气管的腔室，用于支撑要供应的晶片的加热器块 该室的内部，其内部具有加热板的加热器块，用于支撑加热器块的支撑轴和用于提供与加热板的电连接的电线。 支撑轴延伸穿过腔室的底部。 电线在支撑轴内延伸穿过腔室的底部。

公开(公告)号：US07205194B2

公开(公告)日：2007-04-17

申请号：US10874579

申请日：2004-06-24

申请人： Yong-Sun Lee ,  Jae-Min Yu ,  Don-Woo Lee ,  Jung-Hun Cho ,  Chul-Soon Kwon ,  Jung-Ho Moon ,  In-Gu Yoon ,  Jae-Hyun Park

发明人： Yong-Sun Lee ,  Jae-Min Yu ,  Don-Woo Lee ,  Jung-Hun Cho ,  Chul-Soon Kwon ,  Jung-Ho Moon ,  In-Gu Yoon ,  Jae-Hyun Park

IPC分类号： H01L21/336

CPC分类号： H01L29/66825 ,  H01L21/28273 ,  H01L29/42324

摘要： A method of fabricating a flash memory cell having a split gate structure. A sacrificial layer is formed on a floating gate layer formed on a semiconductor substrate. The sacrificial layer is etched to form an opening exposing a portion of the floating gate layer. A gate interlayer insulating layer pattern is formed inside the opening. After removing the sacrificial layer pattern and etching the floating gate layer (using the gate interlayer insulating layer pattern as an etch mask), a floating gate is formed under the gate interlayer insulating layer pattern. A control gate is formed overlapping a portion of the floating gate.

摘要翻译： 一种制造具有分裂栅极结构的闪存单元的方法。 牺牲层形成在形成在半导体衬底上的浮栅上。 牺牲层被蚀刻以形成暴露浮动栅极层的一部分的开口。 在开口内部形成栅极层间绝缘层图案。 在去除牺牲层图案并蚀刻浮栅（使用栅极层间绝缘层图案作为蚀刻掩模）之后，在栅极层间绝缘层图案下方形成浮栅。 控制栅极形成为与浮置栅极的一部分重叠。

公开(公告)号：US06797109B2

公开(公告)日：2004-09-28

申请号：US10235976

申请日：2002-09-06

申请人： Jeong-hyuck Park ,  Hee-duk Kim ,  Jung-hun Cho ,  Jong-wook Choi ,  Sung-bum Cho ,  Young-koo Lee ,  Jin-sung Kim ,  Jang-eun Lee ,  Ju-hyuck Chung ,  Sun-hoo Park ,  Jae-hyun Lee ,  Shin-woo Nam

发明人： Jeong-hyuck Park ,  Hee-duk Kim ,  Jung-hun Cho ,  Jong-wook Choi ,  Sung-bum Cho ,  Young-koo Lee ,  Jin-sung Kim ,  Jang-eun Lee ,  Ju-hyuck Chung ,  Sun-hoo Park ,  Jae-hyun Lee ,  Shin-woo Nam

IPC分类号： H05H100

CPC分类号： H01J37/32431 ,  C23C16/4583 ,  C23C16/4585 ,  C23C16/54 ,  H01J37/32623 ,  H01J37/32642 ,  H01L21/32136 ,  H01L21/6831 ,  H01L21/68735 ,  Y10T117/10

摘要： A process chamber used in the manufacture of a semiconductor device for etching a material layer on a semiconductor wafer includes an electrostatic chuck for holding the semiconductor wafer, and an annular edge ring which surrounds the side of the semiconductor wafer on the electrostatic chuck to prevent the semiconductor wafer from departing from its original position. The annular edge ring has a first side which faces the side of the semiconductor wafer and contacts firmly with the side of the semiconductor wafer.

摘要翻译： 用于制造用于蚀刻半导体晶片上的材料层的半导体器件的处理室包括用于保持半导体晶片的静电卡盘和围绕静电卡盘上的半导体晶片侧的环形边缘环，以防止 半导体晶片从其原始位置脱离。 环形边缘环具有面向半导体晶片的侧面并​​与半导体晶片的侧面牢固接触的​​第一侧。

公开(公告)号：US06464794B1

公开(公告)日：2002-10-15

申请号：US09404631

申请日：1999-09-23

申请人： Jeong-hyuck Park ,  Hee-duk Kim ,  Jung-hun Cho ,  Jong-wook Choi ,  Sung-bum Cho ,  Young-koo Lee ,  Jin-sung Kim ,  Jang-eun Lee ,  Ju-hyuck Chung ,  Sun-hoo Park ,  Jae-hyun Lee ,  Shin-woo Nam

发明人： Jeong-hyuck Park ,  Hee-duk Kim ,  Jung-hun Cho ,  Jong-wook Choi ,  Sung-bum Cho ,  Young-koo Lee ,  Jin-sung Kim ,  Jang-eun Lee ,  Ju-hyuck Chung ,  Sun-hoo Park ,  Jae-hyun Lee ,  Shin-woo Nam

IPC分类号： C23C1600

CPC分类号： H01J37/32431 ,  C23C16/4583 ,  C23C16/4585 ,  C23C16/54 ,  H01J37/32623 ,  H01J37/32642 ,  H01L21/32136 ,  H01L21/6831 ,  H01L21/68735 ,  Y10T117/10

摘要： A process chamber used in the manufacture of a semiconductor device for etching a material layer on a semiconductor wafer includes an electrostatic chuck for holding the semiconductor wafer, and an annular edge ring which surrounds the side of the semiconductor wafer on the electrostatic chuck to prevent the semiconductor wafer from departing from its original position. The annular edge ring has a first side which faces the side of the semiconductor wafer and contacts firmly with the side of the semiconductor wafer.

摘要翻译： 用于制造用于蚀刻半导体晶片上的材料层的半导体器件的处理室包括用于保持半导体晶片的静电卡盘和围绕静电卡盘上的半导体晶片侧的环形边缘环，以防止 半导体晶片从其原始位置脱离。 环形边缘环具有面向半导体晶片的侧面并​​与半导体晶片的侧面牢固接触的​​第一侧。