公开(公告)号：US20110156101A1

公开(公告)日：2011-06-30

申请号：US12979142

申请日：2010-12-27

申请人： Yoshiaki Shimizu ,  Kazuhiko Matsuki

发明人： Yoshiaki Shimizu ,  Kazuhiko Matsuki

IPC分类号： H01L27/118

CPC分类号： H01L27/11807 ,  H01L27/0207

摘要： A semiconductor device may include a plurality of logic circuits connected to each other through input and output terminals thereof. The plurality of logic circuits comprising a first sub-plurality of logic circuits coupled to a first one of different power systems. The first sub-plurality of logic circuits is laid out and adjacent to each other in a first direction. The first sub-plurality of logic circuits includes a first logic circuit and a second logic circuit. The second logic circuit is adjacent to the first logic circuit. The first logic circuit includes a first element comprising a first diffusion layer. The second logic circuit includes a second element comprising the first diffusion layer.

摘要翻译： 半导体器件可以包括通过其输入和输出端子彼此连接的多个逻辑电路。 多个逻辑电路包括耦合到不同电源系统中的第一个的第一子组多个逻辑电路。 逻辑电路的第一子组合在第一方向相互布置并相邻。 第一子逻辑电路包括第一逻辑电路和第二逻辑电路。 第二逻辑电路与第一逻辑电路相邻。 第一逻辑电路包括包括第一扩散层的第一元件。 第二逻辑电路包括包括第一扩散层的第二元件。

公开(公告)号：US20090146319A1

公开(公告)日：2009-06-11

申请号：US12327099

申请日：2008-12-03

申请人： Takamitsu ONDA ,  Kazuhiko MATSUKI

发明人： Takamitsu ONDA ,  Kazuhiko MATSUKI

IPC分类号： H01L23/495

CPC分类号： H01L24/05 ,  H01L22/32 ,  H01L23/60 ,  H01L27/0203 ,  H01L27/0248 ,  H01L2224/02166 ,  H01L2224/05553 ,  H01L2924/01004 ,  H01L2924/01006 ,  H01L2924/01033

摘要： A semiconductor device which can prevent damage to an ESD protection device by pressure when bonding is carried out, while having a pad configuration that can ensure bonding reliability, with the semiconductor device being made as small as possible. A bonding area that is an area for wire bonding with respect to an external electrode pad and a probing area that is an area in which a probe needle is applied when probing, are provided, and the ESD protection device and a discharge path therefor are arranged below the probing area. Arranged below the bonding area are a support via that is a little smaller than the bonding pad, and a support pattern having a size corresponding to the bonding pad and joined to the bonding pad by the support via.

摘要翻译： 一种半导体器件，其能够在进行接合时能够防止由于压力而对ESD保护器件造成损坏的半导体器件，同时具有能够确保接合可靠性的焊盘构造，半导体器件尽可能小。 设置作为与外部电极焊盘进行引线接合的区域的接合区域和在探测时作为探针插入的区域的探测区域，并且设置ESD保护器件及其放电路径 低于探测区域。 在接合区域下方布置有比接合焊盘稍小的支撑通孔，以及具有与接合焊盘相对应的尺寸并且由支撑通孔接合到接合焊盘的支撑图案。

公开(公告)号：US20080005715A1

公开(公告)日：2008-01-03

申请号：US11808366

申请日：2007-06-08

申请人： Yoshiaki Shimizu ,  Kazuhiko Matsuki

发明人： Yoshiaki Shimizu ,  Kazuhiko Matsuki

IPC分类号： G06F17/50

CPC分类号： G06F17/5077

摘要： An automatic wiring method of a semiconductor integrated circuit determines a wiring position based on layout data in which a plurality of cells corresponding to circuit elements of the semiconductor integrated circuit, which comprises the steps of when arranging a predetermined signal line extending in a first direction, extracting one or more coordinates in a second direction orthogonal to the first direction of all connecting terminals selected to be connected to the predetermined signal line among connecting terminals respectively included in the plurality of cells; calculating an average value of the extracted coordinates; and determining a position of the predetermined signal line in the second direction based on the average value.

摘要翻译： 半导体集成电路的自动布线方法基于与半导体集成电路的电路元件相对应的多个单元的布局数据来确定布线位置，其包括以下步骤：当布置沿第一方向延伸的预定信号线时， 在与分别包含在所述多个单元中的连接端子中选择连接到所述预定信号线的所有连接端子的所述第一方向垂直的第二方向上提取一个或多个坐标; 计算提取坐标的平均值; 以及基于所述平均值确定所述预定信号线在所述第二方向上的位置。

公开(公告)号：US20090307648A1

公开(公告)日：2009-12-10

申请号：US12478834

申请日：2009-06-05

申请人： Hayato OOISHI ,  Kazuhiko Matsuki

发明人： Hayato OOISHI ,  Kazuhiko Matsuki

IPC分类号： G06F17/50

CPC分类号： G06F17/5068 ,  G06F17/5077

摘要： A through-hole layout apparatus includes: an extractor extracting an existing through-hole from design data for a semiconductor integrated circuit; a calculator calculating, for each through-hole extracted by the extractor, a layout density of through-holes in a predetermined region; a selector selecting a through-hole at the center of a predetermined region where the layout density is lower than a predetermined value as a target through-hole from among the through-holes extracted by the extractor; and a through-hole adder determining, for each target through-hole selected by the selector, a given position in a predetermined region centered on the target through-hole as a placement position at which a through-hole is to be added.

摘要翻译： 通孔布置装置包括：提取器，从半导体集成电路的设计数据提取现有的通孔; 计算器，对于由所述提取器提取的每个通孔，计算预定区域中的通孔的布局密度; 选择器，从布置密度低于预定值的预定区域的中心处选择通孔，作为从提取器提取的通孔中的目标通孔; 以及通孔加法器，对于由选择器选择的每个目标通孔，确定作为要添加通孔的放置位置的以目标通孔为中心的预定区域中的给定位置。

公开(公告)号：US07923809B2

公开(公告)日：2011-04-12

申请号：US12407250

申请日：2009-03-19

申请人： Takamitsu Onda ,  Kazuhiko Matsuki

发明人： Takamitsu Onda ,  Kazuhiko Matsuki

IPC分类号： H01L29/06

CPC分类号： H01P3/003

摘要： A semiconductor device comprises a semiconductor substrate; a diffusion layer formed on the semiconductor substrate; at least two wiring layers formed opposite to each other over the semiconductor substrate; signal lines for transmitting a signal maintaining a predetermined voltage, each of the signal lines being formed in each of the two wiring layers; shield lines fixed to a constant voltage to shield the signal lines, each of the shield lines being formed adjacent to each of the signal lines in the two wiring layers; and a gate electrode formed over the semiconductor substrate via an insulation film. In the semiconductor device, at least one of the signal lines formed in a lower wiring layer of the at least two wiring layers is electrically connected to the gate electrode opposed in a stacking direction.

摘要翻译： 半导体器件包括半导体衬底; 形成在所述半导体衬底上的扩散层; 在所述半导体衬底上形成为相互相对的至少两个布线层; 用于发送保持预定电压的信号的信号线，每个信号线形成在两个布线层中的每一个中; 屏蔽线固定在恒定电压上以屏蔽信号线，每条屏蔽线与两个布线层中的每个信号线相邻形成; 以及通过绝缘膜形成在半导体衬底上的栅电极。 在半导体器件中，形成在至少两个布线层的下布线层中的信号线中的至少一个电连接到堆叠方向相对的栅电极。

公开(公告)号：US08504964B2

公开(公告)日：2013-08-06

申请号：US12478834

申请日：2009-06-05

申请人： Hayato Ooishi ,  Kazuhiko Matsuki

发明人： Hayato Ooishi ,  Kazuhiko Matsuki

IPC分类号： G06F17/50

CPC分类号： G06F17/5068 ,  G06F17/5077

摘要： A through-hole layout apparatus and method for reducing differences in layout density of through-holes. The through-hole layout apparatus includes an extractor, which extracts an existing through-hole from design data for a semiconductor integrated circuit, a calculator, which calculates a layout density of through-holes in a predetermined region for each through-hole extracted by the extractor, a selector, which selects a through-hole at the center of a predetermined region where the layout density is lower than a predetermined value as a target through-hole from among the through-holes extracted by the extractor and a through-hole adder, which determines a given position in a predetermined region centered on the target through-hole as a placement position at which a through-hole is to be added for each target through-hole selected by the selector.

摘要翻译： 一种用于减小通孔布局密度差异的通孔布置装置和方法。 通孔布置装置包括从半导体集成电路的设计数据中提取现有通孔的提取器，计算器，其针对由所述半导体集成电路提取的每个通孔计算预定区域中的通孔的布局密度 提取器，选择器，其从布置密度低于预定值的预定区域的中心选择通孔，作为目标通孔，从通过提取器提取的通孔和通孔加法器 ，其以在目标通孔为中心的预定区域中的给定位置作为要由选择器选择的每个目标通孔添加通孔的放置位置。

公开(公告)号：US08354696B2

公开(公告)日：2013-01-15

申请号：US12979142

申请日：2010-12-27

申请人： Yoshiaki Shimizu ,  Kazuhiko Matsuki

发明人： Yoshiaki Shimizu ,  Kazuhiko Matsuki

IPC分类号： H01L27/118

CPC分类号： H01L27/11807 ,  H01L27/0207

摘要： A semiconductor device may include a plurality of logic circuits connected to each other through input and output terminals thereof. The plurality of logic circuits comprising a first sub-plurality of logic circuits coupled to a first one of different power systems. The first sub-plurality of logic circuits is laid out and adjacent to each other in a first direction. The first sub-plurality of logic circuits includes a first logic circuit and a second logic circuit. The second logic circuit is adjacent to the first logic circuit. The first logic circuit includes a first element comprising a first diffusion layer. The second logic circuit includes a second element comprising the first diffusion layer.

摘要翻译： 半导体器件可以包括通过其输入和输出端子彼此连接的多个逻辑电路。 多个逻辑电路包括耦合到不同电源系统中的第一个的第一子组多个逻辑电路。 逻辑电路的第一子组合在第一方向相互布置并相邻。 第一子逻辑电路包括第一逻辑电路和第二逻辑电路。 第二逻辑电路与第一逻辑电路相邻。 第一逻辑电路包括包括第一扩散层的第一元件。 第二逻辑电路包括包括第一扩散层的第二元件。

公开(公告)号：US20090237186A1

公开(公告)日：2009-09-24

申请号：US12407250

申请日：2009-03-19

申请人： Takamitsu ONDA ,  Kazuhiko MATSUKI

发明人： Takamitsu ONDA ,  Kazuhiko MATSUKI

IPC分类号： H01P3/08

CPC分类号： H01P3/003

摘要： A semiconductor device comprises a semiconductor substrate; a diffusion layer formed on the semiconductor substrate; at least two wiring layers formed opposite to each other over the semiconductor substrate; signal lines for transmitting a signal maintaining a predetermined voltage, each of the signal lines being formed in each of the two wiring layers; shield lines fixed to a constant voltage to shield the signal lines, each of the shield lines being formed adjacent to each of the signal lines in the two wiring layers; and a gate electrode formed over the semiconductor substrate via an insulation film. In the semiconductor device, at least one of the signal lines formed in a lower wiring layer of the at least two wiring layers is electrically connected to the gate electrode opposed in a stacking direction.

摘要翻译： 半导体器件包括半导体衬底; 形成在所述半导体衬底上的扩散层; 在所述半导体衬底上形成为相互相对的至少两个布线层; 用于发送保持预定电压的信号的信号线，每个信号线形成在两个布线层中的每一个中; 屏蔽线固定在恒定电压上以屏蔽信号线，每条屏蔽线与两个布线层中的每个信号线相邻形成; 以及通过绝缘膜形成在半导体衬底上的栅电极。 在半导体器件中，形成在至少两个布线层的下布线层中的信号线中的至少一个电连接到堆叠方向相对的栅电极。

公开(公告)号：US06330205B2

公开(公告)日：2001-12-11

申请号：US09741419

申请日：2000-12-21

申请人： Yoshiaki Shimizu ,  Kazuhiko Matsuki

发明人： Yoshiaki Shimizu ,  Kazuhiko Matsuki

IPC分类号： G11C1300

CPC分类号： G11C11/4085 ,  G11C8/08

摘要： The present invention provides a semiconductor memory device comprising: memory cells; main decoders decoding address signals sense amplifiers for reading out informations from the memory cells; and word drivers for driving the memory cells, wherein a row address controlled by a single main word line in a basic cell in the word driver, and two of the main word line of the row address are made correspond to a half of lower-order 2-bits of the row address, and a word driver signal is placed inside of the basic cell of the word driver to prevent the word driver signal from being commonly used to adjacent two of the basic cell.

摘要翻译： 本发明提供了一种半导体存储器件，包括：存储单元; 主解码器解码地址信号读出放大器，用于从存储单元读出信息; 以及用于驱动存储单元的字驱动器，其中由字驱动器中的基本单元中的单个主字线控制的行地址和行地址的主字线中的两个对应于低位的一半 2位的行地址和字驱动器信号被放置在字驱动器的基本单元内部，以防止字驱动器信号被普遍用于相邻的两个基本单元。

公开(公告)号：US07994542B2

公开(公告)日：2011-08-09

申请号：US11806451

申请日：2007-05-31

申请人： Hirokazu Ato ,  Kazuhiko Matsuki

发明人： Hirokazu Ato ,  Kazuhiko Matsuki

IPC分类号： H01L27/10

CPC分类号： H01L27/0207

摘要： A semiconductor device of the present invention comprises a logic circuit to which a power supply voltage, a sub-power supply voltage, a ground voltage and a sub-ground voltage are supplied; a driver for generating the sub-power supply voltage and the sub-ground voltage based on the power supply voltage and the ground voltage; a first wiring layer including a sub-power supply line for supplying the sub-power supply voltage and a sub-ground line for supplying the sub-ground voltage; a second wiring layer including source/drain lines for MOS transistors; a third wiring layer including a main power supply line for supplying the power supply voltage and a main ground line for supplying the ground voltage and arranged opposite to the first wiring layer to sandwich the second wiring layer; via structures for connecting the source/drain lines of the second wiring layer to the other layers.

摘要翻译： 本发明的半导体器件包括供电电源电压，副电源电压，接地电压和次地电压的逻辑电路; 用于基于电源电压和接地电压产生副电源电压和次地电压的驱动器; 包括用于提供副电源电压的副电源线的第一布线层和用于提供副地电压的副地线; 包括用于MOS晶体管的源极/漏极线的第二布线层; 第三布线层，包括用于提供电源电压的主电源线和用于提供接地电压并与第一布线层相对布置以夹住第二布线层的主地线; 通孔结构，用于将第二布线层的源极/漏极线连接到其它层。