公开(公告)号：US5315547A

公开(公告)日：1994-05-24

申请号：US960280

申请日：1992-10-13

申请人： Kazuyoshi Shoji ,  Tadashi Muto ,  Yasurou Kubota ,  Koichi Seki ,  Kazuto Izawa ,  Shinji Nabetani, deceased

发明人： Kazuyoshi Shoji ,  Tadashi Muto ,  Yasurou Kubota ,  Koichi Seki ,  Kazuto Izawa ,  Shinji Nabetani, deceased

IPC分类号： G11C16/12 ,  G11C16/16 ,  G11C16/30 ,  G11C7/00

CPC分类号： G11C16/30 ,  G11C16/12 ,  G11C16/16

摘要： In a nonvolatile semiconductor memory device, a high voltage is selectively exerted between a word line to which the control gates of nonvolatile semiconductor memory elements are coupled and a source line to which the sources of the nonvolatile semiconductor memory elements are coupled, whereby charges stored in the floating gates are extracted through the source line. In addition, the nonvolatile semiconductor memory elements to be erased are provided with a source potential having ramp-rate characteristics such that the sources are gradually raised from a low voltage to the high voltage. Thus, the erasure of a predetermined part of the memory array of the memory device becomes possible in accordance with the division of the source lines or that of the word lines, and an excessive intense electric field can be prevented from acting between the floating gates and the sources because a ramp rate is used for the erasing high voltage.

摘要翻译： 在非易失性半导体存储器件中，高电压选择性地施加在与非易失性半导体存储元件的控制栅极耦合的字线和非易失性半导体存储元件的源耦合到的源极线之间，由此存储在 浮动栅极通过源极线提取。 另外，要被擦除的非易失性半导体存储元件被提供有具有斜率特性的源极电位，使得源极从低电压逐渐升高到高电压。 因此，根据源极线或字线的划分，存储器件的存储器阵列的预定部分的擦除成为可能，并且可以防止过大的强电场作用在浮动栅极和 因为使用斜坡率来消除高电压。

公开(公告)号：US07908424B2

公开(公告)日：2011-03-15

申请号：US11802998

申请日：2007-05-29

申请人： Atsushi Shikata ,  Kunihiro Katayama ,  Masato Matsumoto ,  Kazuto Izawa ,  Motoki Kanamori

发明人： Atsushi Shikata ,  Kunihiro Katayama ,  Masato Matsumoto ,  Kazuto Izawa ,  Motoki Kanamori

IPC分类号： G06F13/00 ,  G06F13/28

CPC分类号： G06F13/1668

摘要： A controller 3 of a memory card is a provided with a command decoding circuit 6 for decoding commands issued by a host HT, a command enable register 8 in which the validity or invalidity of the received command, and a command detection signal generating circuit 7 for detecting a valid command on the basis of the result of decoding by the command decoding circuit 6 and a value set by the command enable register 8. If the command enable register 8 receives a validly set command, the command detection signal generating circuit 7 will supply a detection signal to a control unit 4 to execute processing prescribed for each command. the command enable register 8 receives an invalidly set command, no detection signal will be supplied, and the command will be ignored.

摘要翻译： 存储卡的控制器3设置有用于解码由主机HT发出的命令的命令解码电路6，其中接收到的命令的有效性或无效的命令使能寄存器8以及用于接收命令的命令检测信号生成电路7 根据命令解码电路6的解码结果和由命令使能寄存器8设定的值来检测有效命令。如果命令使能寄存器8接收到有效设置的命令，则命令检测信号发生电路7将提供 检测信号发送到控制单元4，以执行对每个命令规定的处理。 命令使能寄存器8接收到无效设置命​​令，不会提供检测信号，并且该命令将被忽略。

公开(公告)号：US20070233956A1

公开(公告)日：2007-10-04

申请号：US11802998

申请日：2007-05-29

申请人： Atsushi Shikata ,  Kunihiro Katayama ,  Masato Matsumoto ,  Kazuto Izawa ,  Motoki Kanamori

发明人： Atsushi Shikata ,  Kunihiro Katayama ,  Masato Matsumoto ,  Kazuto Izawa ,  Motoki Kanamori

IPC分类号： G06F12/00

CPC分类号： G06F13/1668

摘要： A controller 3 of a memory card is a provided with a command decoding circuit 6 for decoding commands issued by a host HT, a command enable register 8 in which the validity or invalidity of the received command, and a command detection signal generating circuit 7 for detecting a valid command on the basis of the result of decoding by the command decoding circuit 6 and a value set by the command enable register 8. If the command enable register 8 receives a validly set command, the command detection signal generating circuit 7 will supply a detection signal to a control unit 4 to execute processing prescribed for each command. the command enable register 8 receives an invalidly set command, no detection signal will be supplied, and the command will be ignored.

摘要翻译： 存储卡的控制器3设置有用于解码由主机HT发出的命令的命令解码电路6，其中接收到的命令的有效性或无效的命令使能寄存器8以及用于接收命令的命令检测信号生成电路7 根据命令解码电路6的解码结果和由命令使能寄存器8设定的值检测有效命令。 如果命令使能寄存器8接收到有效设置的命令，则命令检测信号发生电路7将向控制单元4提供检测信号，以执行对每个命令规定的处理。 命令使能寄存器8接收到无效设置命​​令，不会提供检测信号，并且该命令将被忽略。

公开(公告)号：US5097446A

公开(公告)日：1992-03-17

申请号：US355480

申请日：1989-05-23

申请人： Kazuyoshi Shoji ,  Takaaki Hagiwara ,  Tadashi Muto ,  Shun-ichi Saeki ,  Yasurou Kubota ,  Kazuto Izawa ,  Yoshiaki Kamigaki ,  Shin-ichi Minami ,  Yuko Nabetani

发明人： Kazuyoshi Shoji ,  Takaaki Hagiwara ,  Tadashi Muto ,  Shun-ichi Saeki ,  Yasurou Kubota ,  Kazuto Izawa ,  Yoshiaki Kamigaki ,  Shin-ichi Minami ,  Yuko Nabetani

IPC分类号： G11C16/32 ,  G11C16/34

CPC分类号： G11C16/3477 ,  G11C16/32 ,  G11C16/3468 ,  G11C16/3486

摘要： A time circuit is provided for a nonvolatile memory device which can electrically be written into. When the write operation on a particular memory cell lasting a relatively long period of time is specified from an external device, the memory device stops the write operation on that memory cell, irrespective of the external write operaiton specification, when the time set on the timer circuit has elapsed. The nonvolatile memory device has memory cells, each consisting of a single transistor. The erase operation on the memory cells is controlled according to a current flowing through these memory cells.

摘要翻译： 提供了一种用于可电气写入的非易失性存储器件的时间电路。 当从外部设备指定对特定存储单元持续相当长时间段的写入操作时，无论外部写入操作规范如何，当定时器上设置的时间时，存储器件停止该存储器单元上的写入操作 电路已经过去了 非易失性存储器件具有各自由单个晶体管组成的存储单元。 根据流过这些存储单元的电流来控制对存储单元的擦除操作。