公开(公告)号：US5097446A

公开(公告)日：1992-03-17

申请号：US355480

申请日：1989-05-23

申请人： Kazuyoshi Shoji ,  Takaaki Hagiwara ,  Tadashi Muto ,  Shun-ichi Saeki ,  Yasurou Kubota ,  Kazuto Izawa ,  Yoshiaki Kamigaki ,  Shin-ichi Minami ,  Yuko Nabetani

发明人： Kazuyoshi Shoji ,  Takaaki Hagiwara ,  Tadashi Muto ,  Shun-ichi Saeki ,  Yasurou Kubota ,  Kazuto Izawa ,  Yoshiaki Kamigaki ,  Shin-ichi Minami ,  Yuko Nabetani

IPC分类号： G11C16/32 ,  G11C16/34

CPC分类号： G11C16/3477 ,  G11C16/32 ,  G11C16/3468 ,  G11C16/3486

摘要： A time circuit is provided for a nonvolatile memory device which can electrically be written into. When the write operation on a particular memory cell lasting a relatively long period of time is specified from an external device, the memory device stops the write operation on that memory cell, irrespective of the external write operaiton specification, when the time set on the timer circuit has elapsed. The nonvolatile memory device has memory cells, each consisting of a single transistor. The erase operation on the memory cells is controlled according to a current flowing through these memory cells.

摘要翻译： 提供了一种用于可电气写入的非易失性存储器件的时间电路。 当从外部设备指定对特定存储单元持续相当长时间段的写入操作时，无论外部写入操作规范如何，当定时器上设置的时间时，存储器件停止该存储器单元上的写入操作 电路已经过去了 非易失性存储器件具有各自由单个晶体管组成的存储单元。 根据流过这些存储单元的电流来控制对存储单元的擦除操作。

公开(公告)号：US4972371A

公开(公告)日：1990-11-20

申请号：US203456

申请日：1988-06-07

申请人： Kazuhiro Komori ,  Takaaki Hagiwara ,  Satoshi Meguro ,  Toshiaki Nishimoto ,  Takeshi Wada ,  Kiyofumi Uchibori ,  Tadashi Muto ,  Hitoshi Kume ,  Hideaki Yamamoto ,  Tetsuo Adachi ,  Toshihisa Tsukada ,  Toshiko Koizumi

发明人： Kazuhiro Komori ,  Takaaki Hagiwara ,  Satoshi Meguro ,  Toshiaki Nishimoto ,  Takeshi Wada ,  Kiyofumi Uchibori ,  Tadashi Muto ,  Hitoshi Kume ,  Hideaki Yamamoto ,  Tetsuo Adachi ,  Toshihisa Tsukada ,  Toshiko Koizumi

IPC分类号： G11C16/04 ,  H01L27/115 ,  H01L29/788

CPC分类号： G11C16/0416 ,  H01L27/115 ,  H01L29/7884

摘要： An EEPROM in which a memory cell is constituted by a floating gate electrode, a control gate electrode, a first semiconductor region provided in a main surface portion of the semiconductor substrate on an end side of the gate electrodes to which the data line is connected, and a second semiconductor region provided in a different main surface portion of the semiconductor substrate on an opposing end side of the gate electrodes to which the grounding line is connected. The drain is used differently depending upon the operations for writing the data, reading the data and erasing the data. The impurity concentration in the first semiconductor region is selected to be lower than that of the second semiconductor region, in order to improve writing and erasing characteristics as well as to increase the reading speed.

摘要翻译： 一种EEPROM，其中存储单元由浮置栅电极，控制栅极电极，设置在半导体衬底的主表面部分中的与数据线连接的栅电极的端侧上的第一半导体区域构成， 以及第二半导体区域，设置在与所述接地线连接的所述栅电极的相对端侧的所述半导体衬底的不同主表面部分中。 漏极的使用方式取决于写入数据的操作，读取数据和擦除数据。 选择第一半导体区域中的杂质浓度低于第二半导体区域的杂质浓度，以提高写入和擦除特性以及增加读取速度。

公开(公告)号：US4443718A

公开(公告)日：1984-04-17

申请号：US188740

申请日：1980-09-19

申请人： Takaaki Hagiwara ,  Yuji Yatsuda

发明人： Takaaki Hagiwara ,  Yuji Yatsuda

IPC分类号： H01L27/112 ,  G11C11/41 ,  G11C16/06 ,  G11C16/26 ,  G11C17/00 ,  H01L21/8246 ,  H01L21/8247 ,  H01L29/788 ,  H01L29/792 ,  H03K19/0185 ,  H03K19/0944 ,  G11C7/06 ,  G11C11/40

CPC分类号： H03K19/09443 ,  G11C16/26 ,  H03K19/018507

摘要： A nonvolatile semiconductor memory including a memory matrix having a plurality of memory cells with nonvolatile memory elements and arranged in the form of a matrix, a selecting circuit for selecting a desired memory cell from the memory matrix, and a read-out circuit for reading out the information stored in the selected memory cell. The read-out circuit includes a sense amplifier and an output buffer. The sensed amplifier includes an inverter having a load element to which a supply voltage is applied and a selected memory cell acting as a driver element. The output buffer includes a level shift circuit for shifting the level of an output signal voltage from the sense amplifier with the level shift circuit including a stabilizing circuit for stabilizing the level of the shifted signal voltage during fluctuations in the supply voltage. An output driver circuit is provided for receiving the shifted signal voltage from the level shift circuit.

摘要翻译： 一种非易失性半导体存储器，包括具有多个具有非易失性存储元件的存储单元并以矩阵形式布置的存储器矩阵，用于从存储矩阵中选择所需存储单元的选择电路和用于读出的读出电路 存储在所选存储单元中的信息。 读出电路包括读出放大器和输出缓冲器。 感测的放大器包括具有施加电源电压的负载元件和用作驱动器元件的选择的存储器单元的逆变器。 输出缓冲器包括电平移位电路，用于通过电平移位电路来移位来自读出放大器的输出信号电压的电平，该电平移位电路包括用于在电源电压波动期间稳定移位信号电压电平的稳定电路。 提供一个输出驱动器电路，用于接收来自电平移位电路的移位信号电压。

公开(公告)号：US4264376A

公开(公告)日：1981-04-28

申请号：US66795

申请日：1979-08-15

申请人： Yuji Yatsuda ,  Shinichi Minami ,  Ryuji Kondo ,  Takaaki Hagiwara ,  Yokichi Itoh

发明人： Yuji Yatsuda ,  Shinichi Minami ,  Ryuji Kondo ,  Takaaki Hagiwara ,  Yokichi Itoh

IPC分类号： H01L27/112 ,  G11C16/04 ,  H01L21/28 ,  H01L21/30 ,  H01L21/336 ,  H01L21/8246 ,  H01L21/8247 ,  H01L29/51 ,  H01L29/788 ,  H01L29/792 ,  H01L21/324

CPC分类号： H01L21/28185 ,  G11C16/0466 ,  H01L21/28202 ,  H01L21/28211 ,  H01L21/3003 ,  H01L29/513 ,  H01L29/518 ,  H01L29/66833 ,  H01L29/792 ,  Y10S438/909

摘要： A metal-silicon nitride-silicon oxide-substrate (MNOS) type nonvolatile memory device is disclosed. After the silicon nitride film has been formed, the heat treatment in the hydrogen atmosphere is performed. As a result of this heat treatment, the degradation of the memory retention characteristic is prevented so that a nonvolatile memory device having a silicon gate can be obtained which is comparable to a conventional nonvolatile memory device having an aluminum gate.

摘要翻译： 公开了一种金属 - 氮化硅 - 氧化硅 - 衬底（MNOS）型非易失性存储器件。 在形成氮化硅膜之后，进行氢气氛中的热处理。 作为这种热处理的结果，防止存储器保持特性的劣化，从而可以获得与具有铝栅极的常规非易失性存储器件相当的具有硅栅极的非易失性存储器件。

公开(公告)号：US20120251391A1

公开(公告)日：2012-10-04

申请号：US13513884

申请日：2010-12-20

申请人： Takaaki Hagiwara ,  Yoshiyuki Tanaka ,  Kazunori Yamazawa

发明人： Takaaki Hagiwara ,  Yoshiyuki Tanaka ,  Kazunori Yamazawa

IPC分类号： G01N35/00

CPC分类号： G01N35/00722 ,  G01N35/00584 ,  G01N35/1004 ,  G01N35/1009 ,  G01N2035/00891 ,  G01N2035/1013 ,  Y10T436/11

摘要： An automatic analyzer comprises selection means for selecting whether a preparatory operation, specified from a plurality of analysis preparation processes of the automatic analyzer, should be executed in an initial process at the powering on of the analyzer or after the start of the actual analysis (i.e., in parallel with the sample analysis operation). For example, the automatic analyzer is equipped with means which allows the analyzer to execute a “system liquid replacement operation”, a “sample nozzle pressure sensor checking operation”, a “reaction vessel discarding operation” and a “pre-cleaning liquid replacement operation” which among various operations that are executed in the preparation process in conventional immunological analyzing apparatus in processes other than the preparation process.

摘要翻译： 一种自动分析器，包括选择装置，用于选择是否应在分析仪上电或在实际分析开始之后的初始处理中执行从自动分析仪的多个分析准备处理中指定的预备操作（即 ，与样本分析操作并行）。 例如，自动分析装置配备有使分析装置执行系统液体更换动作，试样喷嘴压力传感器检查动作，反应容器废弃操作以及在执行的各种操作中的预清洗液体更换动作的装置 在制备过程以外的方法的常规免疫分析装置的制备过程中。

公开(公告)号：US5340760A

公开(公告)日：1994-08-23

申请号：US992473

申请日：1992-12-15

申请人： Kazuhiro Komori ,  Satoshi Meguro ,  Takaaki Hagiwara ,  Hitoshi Kume ,  Toshihisa Tsukada ,  Hideaki Yamamoto

发明人： Kazuhiro Komori ,  Satoshi Meguro ,  Takaaki Hagiwara ,  Hitoshi Kume ,  Toshihisa Tsukada ,  Hideaki Yamamoto

IPC分类号： A01H5/02 ,  H01L27/06 ,  H01L27/105 ,  H01L29/788 ,  H01L21/335

CPC分类号： A01H5/02 ,  H01L27/105 ,  H01L29/7885 ,  H01L29/7886 ,  H01L27/0688

摘要： This invention discloses EEPROM which increases an erasing voltage V.sub.pp to be applied in a data write cycle by increasing an avalanche breakdown voltage between a source region and a semiconductor substrate in order to improve erasing efficiency, and employs a structure which strengthens the electric field at the edge of a drain region in order to let hot carrier be easily generated and to improve writing efficiency.

摘要翻译： 本发明公开了一种EEPROM，其通过增加源极区域和半导体衬底之间的雪崩击穿电压来增加在数据写入周期中施加的擦除电压Vpp，以提高擦除效率，并采用这样的结构， 边缘，以便容易地产生热载体并提高写入效率。

公开(公告)号：US5252505A

公开(公告)日：1993-10-12

申请号：US820933

申请日：1992-01-15

申请人： Yuji Yatsuda ,  Takaaki Hagiwara ,  Ryuji Kondo ,  Shinichi Minami ,  Yokichi Itoh

发明人： Yuji Yatsuda ,  Takaaki Hagiwara ,  Ryuji Kondo ,  Shinichi Minami ,  Yokichi Itoh

IPC分类号： G11C11/34 ,  G11C16/04 ,  H01L23/522 ,  H01L27/105 ,  H01L21/336 ,  H01L27/088 ,  H01L27/112 ,  H01L27/115

CPC分类号： H01L27/105 ,  G11C16/0466 ,  H01L23/522 ,  H01L2924/0002 ,  H01L2924/3011

摘要： The present invention deals with a semiconductor memory circuit device, in which a memory array portion of a rectangular shape consisting of semiconductor non-volatile memory elements is formed on a main surface of the semiconductor substrate, a low voltage driver circuit (decoder) is formed along a side of the memory array portion, and a high voltage driver circuit is formed along an opposite side of the memory array portion. This permits a reduction in word line length and avoids crossing of the word lines to permit increased operation speed and, particularly, increased reading speed.

摘要翻译： 本发明涉及一种半导体存储器电路器件，其中在半导体衬底的主表面上形成由半导体非易失性存储元件组成的矩形存储器阵列部分，形成低电压驱动电路（解码器） 沿着存储器阵列部分的一侧，并且沿着存储器阵列部分的相对侧形成高压驱动电路。 这允许字线长度减小并且避免字线的交叉以允许增加的操作速度，特别是增加的读取速度。

公开(公告)号：US5114870A

公开(公告)日：1992-05-19

申请号：US351847

申请日：1989-05-15

申请人： Yuji Yatsuda ,  Takaaki Hagiwara ,  Ryuji Kondo ,  Shinichi Minami ,  Yokichi Itoh

发明人： Yuji Yatsuda ,  Takaaki Hagiwara ,  Ryuji Kondo ,  Shinichi Minami ,  Yokichi Itoh

IPC分类号： H01L27/112 ,  G11C11/34 ,  G11C14/00 ,  G11C16/04 ,  H01L21/76 ,  H01L21/8246 ,  H01L21/8247 ,  H01L27/10 ,  H01L27/105 ,  H01L27/115 ,  H01L29/78 ,  H01L29/788 ,  H01L29/792

CPC分类号： H01L29/78 ,  G11C16/0466 ,  H01L27/105 ,  Y10S148/07 ,  Y10S148/117 ,  Y10S148/141

摘要： The present invention deals with a semiconductor memory circuit device, in which a memory array portion of a rectangular shape consisting of semiconductor non-volatile memory elements is formed on a main surface of the semiconductor substrate, a low voltage driver circuit (decoder) is formed along a side of the memory array portion, and a high voltage driver circuit is formed along an opposite side of the memory array portion. This permits a reduction in word line length and avoids crossing of the word lines to permit increased operation speed and, particularly, increased reading speed.

公开(公告)号：US5079603A

公开(公告)日：1992-01-07

申请号：US517386

申请日：1990-04-30

申请人： Kazuhiro Komori ,  Satoshi Meguro ,  Takaaki Hagiwara ,  Hitoshi Kume ,  Toshihisa Tsukada ,  Hideaki Yamamoto

发明人： Kazuhiro Komori ,  Satoshi Meguro ,  Takaaki Hagiwara ,  Hitoshi Kume ,  Toshihisa Tsukada ,  Hideaki Yamamoto

IPC分类号： H01L27/112 ,  H01L21/8246 ,  H01L21/8247 ,  H01L27/06 ,  H01L27/10 ,  H01L27/105 ,  H01L27/115 ,  H01L29/78 ,  H01L29/788 ,  H01L29/792

CPC分类号： H01L29/7886 ,  H01L27/105 ,  H01L27/0688

摘要： This invention discloses an EEPROM which increases an erasing voltage V.sub.pp to be applied during a data write cycle by increasing an avalanche breakdown voltage between a source region and a semiconductor substrate in the memory cell transistor in order to improve the erasing efficiency, and employs a structure which strengthens the electric field at the edge of a drain region in order to let hot carriers be easily generated and to thereby improve writing efficiency.

摘要翻译： 本发明公开了一种EEPROM，其通过增加存储单元晶体管中的源极区域和半导体衬底之间的雪崩击穿电压来增加在数据写入周期期间施加的擦除电压Vpp，以提高擦除效率，并采用结构 这加强了漏极区域的边缘处的电场，以便容易地产生热载流子，从而提高写入效率。

公开(公告)号：US4656607A

公开(公告)日：1987-04-07

申请号：US632317

申请日：1984-07-19

申请人： Takaaki Hagiwara ,  Toru Kaga ,  Hiroo Masuda

发明人： Takaaki Hagiwara ,  Toru Kaga ,  Hiroo Masuda

IPC分类号： H01L27/112 ,  G11C11/40 ,  G11C11/404 ,  G11C14/00 ,  G11C16/04 ,  H01L21/8246 ,  H01L21/8247 ,  H01L27/10 ,  H01L29/788 ,  H01L29/792

CPC分类号： H01L29/7881 ,  G11C11/404 ,  G11C16/0408

摘要： In a semiconductor memory made up of semiconductor memory elements, each consisting of a transistor of an MOS structure which has a charge-storage layer and which is formed on a semiconductor substrate, the improvement wherein a switching element is provided so that positive or negative charge can be stored or discharged from the charge-storage layer in a mode for writing data, and the charge-storage layer can be allowed to float electrically when in a mode for reading data.

摘要翻译： 在由半导体存储元件构成的半导体存储器中，每个由具有电荷存储层的MOS结构的晶体管构成，并形成在半导体衬底上，其特征在于，提供一种开关元件，使得正或负电荷 可以以用于写入数据的模式从电荷存储层存储或放电，并且当处于读取数据的模式时，可以允许电荷存储层电浮动。