公开(公告)号：US5121284A

公开(公告)日：1992-06-09

申请号：US574199

申请日：1990-08-27

申请人： Keith K. Onodera ,  Shu-ing Ju

发明人： Keith K. Onodera ,  Shu-ing Ju

IPC分类号： H01H47/32

CPC分类号： H01H47/325

摘要： A drive circuit suitable for driving an inductive load such as an isolation transformer is disclosed having a driver stage and associated feedback circuitry. The driver stage has at least one output for connecting to the load and is switchable between a drive mode and an idle mode of operation. In the drive mode of operation, the driver stage produces a data output signal at the output which corresponds to a data input signal received by the driver stage. In the idle mode, the driver stage produces an idle signal, in response to a control signal, which functions to discharge the conductive load. The feedback circuit produces the control signal in response to the idle signal and adjusts the control signal so that the idle output signal will approach a predetermined neutral level. The inductor will proceed to discharge and, once discharged, will shift the idle voltage. The shift in voltage will cause the feedback action to terminte, thereby preventing the feedback action from introducing charging current into the inductor which would adversely effect the transmission of further data.

摘要翻译： 公开了一种适于驱动诸如隔离变压器的感性负载的驱动电路，其具有驱动器级和相关联的反馈电路。 驱动级具有至少一个用于连接到负载的输出，并且可以在驱动模式和空闲操作模式之间切换。 在驱动模式下，驱动级在输出端产生数据输出信号，该信号对应于由驱动级接收的数据输入信号。 在空闲模式下，驱动器级响应于控制信号产生空载信号，该控制信号用于对导电负载进行放电。 反馈电路响应于空闲信号产生控制信号并调节控制信号，使得空转输出信号将接近预定的中性电平。 电感将进行放电，一旦放电，将会转移空闲电压。 电压的偏移将导致反馈动作到端子，从而防止反馈动作将电流引入到电感器中，这将不利地影响进一步数据的传输。

公开(公告)号：US07865150B2

公开(公告)日：2011-01-04

申请号：US11768783

申请日：2007-06-26

申请人： William J. McFarland ,  Keith K. Onodera ,  Arie Shor ,  David K. Su ,  Manolis Terrovitis ,  John S. Thomson ,  Masoud Zaragari

发明人： William J. McFarland ,  Keith K. Onodera ,  Arie Shor ,  David K. Su ,  Manolis Terrovitis ,  John S. Thomson ,  Masoud Zaragari

IPC分类号： H04B1/44

CPC分类号： H04W88/06 ,  H03H7/0153 ,  H03H7/48 ,  H04B7/0602 ,  H04B7/0805 ,  H04W84/12

摘要： A dual band radio is constructed using a primary and secondary transceiver. The primary transceiver is a complete radio that is operational in a stand alone configuration. The secondary transceiver is a not a complete radio and is configured to re-use components such as fine gain control and fine frequency stepping of the primary transceiver to produce operational frequencies of the secondary transceiver. The primary transceiver acts like an intermediate frequency device for the secondary transceiver. Switches are utilized to divert signals to/from the primary transceiver from/to the secondary transceiver. The switches are also configured to act as gain control devices. Antennas are selected using either wideband or narrowband antenna switches that are configured as a diode bridge having high impedance at operational frequencies on control lines that bias the diodes.

摘要翻译： 使用主要和次要收发器构建双频无线电。 主收发器是在独立配置中可操作的完整无线电。 辅助收发器不是完整的无线电设备，并被配置为重新使用诸如主收发器的精细增益控制和精细频率步进的组件来产生次级收发器的操作频率。 主收发器像次级收发器的中频设备一样工作。 开关用于将信号从/从主收发器转发到/从辅助收发器。 开关还被配置为用作增益控制装置。 使用宽带或窄带天线开关选择天线，该开关被配置为在偏置二极管的控制线上的工作频率处具有高阻抗的二极管桥。

公开(公告)号：US07233205B2

公开(公告)日：2007-06-19

申请号：US11078246

申请日：2005-03-11

申请人： Keith K. Onodera

发明人： Keith K. Onodera

IPC分类号： H03F3/45

CPC分类号： H03F3/45188 ,  H03F2203/45072 ,  H03F2203/45244 ,  H03F2203/45292 ,  H03F2203/45464 ,  H03F2203/45638

摘要： A differential amplifier can include input transistors for receiving a differential input signal and an inductor connected to the input transistors. The inductor can protect a voltage supply from radio frequency in the differential input signal. The accuracy of this differential amplifier can be significantly improved by including a bias network. This bias network advantageously allows a bias current in the input transistors to be set independently of a voltage drop across the inductor.

摘要翻译： 差分放大器可以包括用于接收差分输入信号的输入晶体管和连接到输入晶体管的电感器。 电感器可以保护差分输入信号中的射频电压。 通过包括偏置网络可以显着提高该差分放大器的精度。 该偏置网络有利地允许输入晶体管中的偏置电流被设置为独立于电感器两端的电压降。

公开(公告)号：US5543754A

公开(公告)日：1996-08-06

申请号：US321242

申请日：1994-10-11

申请人： Keith K. Onodera

发明人： Keith K. Onodera

IPC分类号： H03L7/099

CPC分类号： H03L7/0991

摘要： A system including a reference oscillator, a controlled oscillator, a digital phase detector, and a digital loop filter uses a method for matching a first oscillation frequency of the controlled oscillator with a second oscillation frequency of the reference oscillator by variably selecting different capacitances and/or resistances of the controlled oscillator using switches. The first and second oscillation frequencies are provided to the digital phase detector, where they are compared to determine an output signal which is indicative of the difference between the first and second frequencies. The output signal is transmitted to a digital loop filter, which converts the output signal into control words. The control words are sent to the controlled oscillator so that the first oscillation frequency can be varied as needed. The controlled oscillator may be a capacitor controlled oscillator (CCO), a resistor controlled oscillator (RCO), or a resistor-capacitor controlled oscillator (RCCO).

摘要翻译： 包括参考振荡器，受控振荡器，数字相位检测器和数字环路滤波器的系统使用通过可变地选择不同电容和/或频率来匹配受控振荡器的第一振荡频率与参考振荡器的第二振荡频率的方法， 或使用开关的受控振荡器的电阻。 将第一和第二振荡频率提供给数字相位检测器，在那里将它们进行比较以确定表示第一和第二频率之间差异的输出信号。 输出信号被传送到数字环路滤波器，它将输出信号转换为控制字。 控制字被发送到受控振荡器，使得第一振荡频率可以根据需要变化。 受控振荡器可以是电容控制振荡器（CCO），电阻控制振荡器（RCO）或电阻 - 电容控制振荡器（RCCO）。

公开(公告)号：US4794281A

公开(公告)日：1988-12-27

申请号：US822083

申请日：1986-01-24

申请人： Keith K. Onodera ,  Alex B. Djenguerian

发明人： Keith K. Onodera ,  Alex B. Djenguerian

IPC分类号： H03K19/00 ,  H03K19/013 ,  H03K19/088 ,  H03K3/33 ,  H03K5/13 ,  H03K17/16

CPC分类号： H03K19/001 ,  H03K19/0136

摘要： A totem-pole transistor circuit in the output stage of a logic device includes, in the base circuit of the current sink transistor, a discharge transistor responsive to each transition of a circuit input signal for discharging the parasitic base capacitance of the sink transistor, and a circuit for delaying the delivery of the input signal to the discharge transistor. The delay results in postponing the transition of the discharge transistor from one operational state to another. This causes the transitions of the discharge transistor to lag the transitions of the totem-pole pair which occur simultaneously with input signal changes. Thus, the discharge transistor is held on for a period of time sufficient to discharge the parasitic capacitance when the current-sink transistor turns off. This speeds up the turn-off of the sink transistor. After the period elapses, the discharge transistor turns off. Then, when base current is supplied to the current-sink transistor to turn it on, the discharge transistor is held off for an amount of time during which all of the base current is provided to the current-sink transistor, causing it to be quickly switched on. Then the discharge transistor is turned on, permitting it to discharge the parasitic capacitance of the current-sink transistor at the next input signal transition.

摘要翻译： 在逻辑器件的输出级中的图腾柱晶体管电路包括在电流吸收晶体管的基极电路中，对放电晶体管的寄生基极电容进行放电的电路输入信号的每个转变进行响应的放电晶体管，以及 用于延迟将输入信号传送到放电晶体管的电路。 延迟导致放电晶体管从一个操作状态转变到另一个操作状态。 这导致放电晶体管的转变滞后于与输入信号变化同时发生的图腾柱对的转变。 因此，放电晶体管保持导通一段时间，足以在导通晶体管截止时对寄生电容进行放电。 这将加速接收晶体管的关断。 经过一段时间后，放电晶体管截止。 然后，当将基极电流提供给电流沉降晶体管以使其导通时，放电晶体管被截止一段时间，在该时间期间，所有基极电流被提供给电流沉降晶体管，使得其快速 切换到。 然后放电晶体管导通，允许放电晶体管在下一个输入信号转变时放电电流吸收晶体管的寄生电容。