公开(公告)号：US06799246B1

公开(公告)日：2004-09-28

申请号：US08991234

申请日：1997-12-16

Applicant: Adrian P. Wise ,  Kevin Douglas Dewar ,  Anthony Mark Jones ,  Martin William Sotheran ,  Colin Smith ,  Helen Rosemary Finch ,  Anthony Peter J. Claydon ,  Donald W. Walker Patterson ,  Mark Barnes ,  Andrew Peter Kuligowski ,  William Philip Robbins ,  Nicholas Birch ,  David Andrew Barnes

Inventor： Adrian P. Wise ,  Kevin Douglas Dewar ,  Anthony Mark Jones ,  Martin William Sotheran ,  Colin Smith ,  Helen Rosemary Finch ,  Anthony Peter J. Claydon ,  Donald W. Walker Patterson ,  Mark Barnes ,  Andrew Peter Kuligowski ,  William Philip Robbins ,  Nicholas Birch ,  David Andrew Barnes

IPC: G06F1208

CPC classification number: H04N21/4307 ,  G06F12/0207 ,  G06F12/04 ,  G06F13/16 ,  G06F13/28 ,  H04N19/13 ,  H04N19/42 ,  H04N19/423 ,  H04N19/61 ,  H04N19/91 ,  H04N21/4305 ,  H04N21/44004

Abstract: A memory interface for connecting a bus to memory comprises an input, a buffer, an address input, a generator, and a writer. The input receives a plurality of data words from the bus. The buffer buffers the data words received from the bus. The address input receives from the bus addresses associated with the plurality of data words. The generator generates a series of addresses in the memory into which the buffered data words may be written. The series of addresses are derived from the received addresses. The writer writes the buffered data words into the memory at the generated addresses.

Abstract translation: 用于将总线连接到存储器的存储器接口包括输入，缓冲器，地址输入，发生器和写入器。 输入从总线接收多个数据字。 缓冲器缓冲从总线接收的数据字。 地址输入从与多个数据字相关联的总线地址接收。 发生器在存储器中产生一系列可以写入缓冲数据字的地址。 该地址系列从接收到的地址中导出。 写入器将生成的地址将缓冲的数据字写入存储器。