公开(公告)号：US5805914A

公开(公告)日：1998-09-08

申请号：US479279

申请日：1995-06-07

申请人： Adrian Philip Wise ,  Martin William Sotheran ,  William Philip Robbins ,  Anthony Peter John Claydon ,  Kevin James Boyd ,  Helen Rosemary Finch

发明人： Adrian Philip Wise ,  Martin William Sotheran ,  William Philip Robbins ,  Anthony Peter John Claydon ,  Kevin James Boyd ,  Helen Rosemary Finch

IPC分类号： G06F13/38 ,  G06F15/00

CPC分类号： G06F13/38 ,  G06F15/00

摘要： A multi-standard video decompression apparatus has a plurality of stages interconnected by a two-wire interface arranged as a pipeline processing machine. Control tokens and DATA Tokens pass over the single two-wire interface for carrying both control and data in token format. A token decode circuit is positioned in certain of the stages for recognizing certain of the tokens as control tokens pertinent to that stage and for passing unrecognized control tokens along the pipeline. Reconfiguration processing circuits are positioned in selected stages and are responsive to a recognized control token for reconfiguring such stage to handle an identified DATA Token. A wide variety of unique supporting subsystem circuitry and processing techniques are disclosed for implementing the system.

公开(公告)号：US06799246B1

公开(公告)日：2004-09-28

申请号：US08991234

申请日：1997-12-16

申请人： Adrian P. Wise ,  Kevin Douglas Dewar ,  Anthony Mark Jones ,  Martin William Sotheran ,  Colin Smith ,  Helen Rosemary Finch ,  Anthony Peter J. Claydon ,  Donald W. Walker Patterson ,  Mark Barnes ,  Andrew Peter Kuligowski ,  William Philip Robbins ,  Nicholas Birch ,  David Andrew Barnes

发明人： Adrian P. Wise ,  Kevin Douglas Dewar ,  Anthony Mark Jones ,  Martin William Sotheran ,  Colin Smith ,  Helen Rosemary Finch ,  Anthony Peter J. Claydon ,  Donald W. Walker Patterson ,  Mark Barnes ,  Andrew Peter Kuligowski ,  William Philip Robbins ,  Nicholas Birch ,  David Andrew Barnes

IPC分类号： G06F1208

CPC分类号： H04N21/4307 ,  G06F12/0207 ,  G06F12/04 ,  G06F13/16 ,  G06F13/28 ,  H04N19/13 ,  H04N19/42 ,  H04N19/423 ,  H04N19/61 ,  H04N19/91 ,  H04N21/4305 ,  H04N21/44004

摘要： A memory interface for connecting a bus to memory comprises an input, a buffer, an address input, a generator, and a writer. The input receives a plurality of data words from the bus. The buffer buffers the data words received from the bus. The address input receives from the bus addresses associated with the plurality of data words. The generator generates a series of addresses in the memory into which the buffered data words may be written. The series of addresses are derived from the received addresses. The writer writes the buffered data words into the memory at the generated addresses.

摘要翻译： 用于将总线连接到存储器的存储器接口包括输入，缓冲器，地址输入，发生器和写入器。 输入从总线接收多个数据字。 缓冲器缓冲从总线接收的数据字。 地址输入从与多个数据字相关联的总线地址接收。 发生器在存储器中产生一系列可以写入缓冲数据字的地址。 该地址系列从接收到的地址中导出。 写入器将生成的地址将缓冲的数据字写入存储器。

公开(公告)号：US5821885A

公开(公告)日：1998-10-13

申请号：US473813

申请日：1995-06-07

申请人： Adrian P. Wise ,  Kevin D. Dewar ,  Anthony Mark Jones ,  Martin William Sotheran ,  Colin Smith ,  Helen Rosemary Finch ,  Anthony Peter John Claydon ,  Donald William Patterson ,  Mark Barnes ,  Andrew Peter Kuligowski ,  William P. Robbins ,  Nicholas Birch ,  David Andrew Barnes

发明人： Adrian P. Wise ,  Kevin D. Dewar ,  Anthony Mark Jones ,  Martin William Sotheran ,  Colin Smith ,  Helen Rosemary Finch ,  Anthony Peter John Claydon ,  Donald William Patterson ,  Mark Barnes ,  Andrew Peter Kuligowski ,  William P. Robbins ,  Nicholas Birch ,  David Andrew Barnes

IPC分类号： H04N5/92 ,  G06F3/14 ,  G06F12/00 ,  G06F12/02 ,  G06F12/04 ,  G06F12/06 ,  G06F12/08 ,  G06F13/00 ,  G06F13/16 ,  G06F13/28 ,  G06F13/37 ,  G06T9/00 ,  G11B7/00 ,  G11B27/10 ,  H03M7/30 ,  H03M7/40 ,  H03M7/42 ,  H04L7/00 ,  H04L7/08 ,  H04L12/433 ,  H04N7/26 ,  H04N7/32 ,  H04N7/50 ,  H04N7/52

CPC分类号： H04N21/4307 ,  G06F12/0207 ,  G06F13/16 ,  G06F13/28 ,  H04N19/42 ,  H04N19/423 ,  H04N19/61 ,  H04N21/4305 ,  H04N21/44004 ,  G06F12/04 ,  H04N19/13 ,  H04N19/91

摘要： An MPEG video decompression method and apparatus utilizing a plurality of stages interconnected by a two-wire interface arranged as a pipeline processing machine. Control tokens and DATA Tokens pass over the single two-wire interface for carrying both control and data in token format. A token decode circuit is positioned in certain of the stages for recognizing certain of the tokens as control tokens pertinent to that stage and for passing unrecognized control tokens along the pipeline. Reconfiguration processing circuits are positioned in selected stages and are responsive to a recognized control token for reconfiguring such stage to handle an identified DATA Token. A wide variety of unique supporting subsystem circuitry and processing techniques are disclosed for implementing the system, including memory addressing, transforming data using a common processing block, time synchronization, asynchronous swing buffering, storing of video information, a parallel Huffman decoder, and the like.

公开(公告)号：US5740460A

公开(公告)日：1998-04-14

申请号：US481772

申请日：1995-06-07

申请人： Adrian P. Wise ,  Kevin D. Dewar ,  Anthony Mark Jones ,  Martin William Sotheran ,  Colin Smith ,  Helen Rosemary Finch ,  Anthony Peter John Claydon ,  Donald William Patterson ,  Mark Barnes ,  Andrew Peter Kuligowski ,  William P. Robbins ,  Nicholas Birch ,  David Andrew Barnes

发明人： Adrian P. Wise ,  Kevin D. Dewar ,  Anthony Mark Jones ,  Martin William Sotheran ,  Colin Smith ,  Helen Rosemary Finch ,  Anthony Peter John Claydon ,  Donald William Patterson ,  Mark Barnes ,  Andrew Peter Kuligowski ,  William P. Robbins ,  Nicholas Birch ,  David Andrew Barnes

IPC分类号： H04N5/92 ,  G06F3/14 ,  G06F12/00 ,  G06F12/02 ,  G06F12/04 ,  G06F12/06 ,  G06F12/08 ,  G06F13/00 ,  G06F13/16 ,  G06F13/28 ,  G06F13/37 ,  G06T9/00 ,  G11B7/00 ,  G11B27/10 ,  H03M7/30 ,  H03M7/40 ,  H03M7/42 ,  H04L7/00 ,  H04L7/08 ,  H04L12/433 ,  H04N7/26 ,  H04N7/32 ,  H04N7/50 ,  H04N7/52 ,  G06F15/66

CPC分类号： H04N21/4307 ,  G06F12/0207 ,  G06F13/16 ,  G06F13/28 ,  H04N19/42 ,  H04N19/423 ,  H04N19/61 ,  H04N21/4305 ,  H04N21/44004 ,  G06F12/04 ,  H04N19/13 ,  H04N19/91

摘要： An MPEG video decompression method and apparatus utilizing a plurality of stages interconnected by a two-wire interface arranged as a pipeline processing machine. Control tokens and DATA Tokens pass over the single two-wire interface for carrying both control and data in token format. A token decode circuit is positioned in certain of the stages for recognizing certain of the tokens as control tokens pertinent to that stage and for passing unrecognized control tokens along the pipeline. Reconfiguration processing circuits are positioned in selected stages and are responsive to a recognized control token for reconfiguring such stage to handle an identified DATA Token. A wide variety of unique supporting subsystem circuitry and processing techniques are disclosed for implementing the system, including memory addressing, transforming data using a common processing block, time synchronization, asynchronous swing buffering, storing of video information, a parallel Huffman decoder, and the like.

摘要翻译： 一种MPEG视频解压缩方法和装置，利用被布置为流水线处理机的两线接口互连的多个级。 控制令牌和数据令牌通过单个双线接口，以承载格式携带控制和数据。 令牌解码电路位于某些阶段，用于将某些令牌识别为与该级相关的控制令牌，并沿着管道传递未被识别的控制令牌。 重新配置处理电路定位在选定的阶段，并且响应于识别的控制令牌，以重新配置这样的阶段来处理所识别的数据令牌。 公开了各种独特的支持子系统电路和处理技术，用于实现系统，包括存储器寻址，使用公共处理块变换数据，时间同步，异步摆动缓冲，存储视频信息，并行霍夫曼解码器等 。

公开(公告)号：US5768629A

公开(公告)日：1998-06-16

申请号：US479910

申请日：1995-06-07

申请人： Adrian P. Wise ,  Kevin D. Dewar ,  Anthony Mark Jones ,  Martin William Sotheran ,  Colin Smith ,  Helen Rosemary Finch ,  Anthony Peter John Claydon ,  Donald William Patterson ,  Mark Barnes ,  Andrew Peter Kuligowski ,  William P. Robbins ,  Nicholas Birch ,  David Andrew Barnes

发明人： Adrian P. Wise ,  Kevin D. Dewar ,  Anthony Mark Jones ,  Martin William Sotheran ,  Colin Smith ,  Helen Rosemary Finch ,  Anthony Peter John Claydon ,  Donald William Patterson ,  Mark Barnes ,  Andrew Peter Kuligowski ,  William P. Robbins ,  Nicholas Birch ,  David Andrew Barnes

IPC分类号： H04N5/92 ,  G06F3/14 ,  G06F12/00 ,  G06F12/02 ,  G06F12/04 ,  G06F12/06 ,  G06F12/08 ,  G06F13/00 ,  G06F13/16 ,  G06F13/28 ,  G06F13/37 ,  G06T9/00 ,  G11B7/00 ,  G11B27/10 ,  H03M7/30 ,  H03M7/40 ,  H03M7/42 ,  H04L7/00 ,  H04L7/08 ,  H04L12/433 ,  H04N7/26 ,  H04N7/32 ,  H04N7/50 ,  H04N7/52

CPC分类号： H04N21/4307 ,  G06F12/0207 ,  G06F13/16 ,  G06F13/28 ,  H04N19/42 ,  H04N19/423 ,  H04N19/61 ,  H04N21/4305 ,  H04N21/44004 ,  G06F12/04 ,  H04N19/13 ,  H04N19/91

摘要： An MPEG video decompression method and apparatus utilizing a plurality of stages interconnected by a two-wire interface arranged as a pipeline processing machine. Control tokens and DATA Tokens pass over the single two-wire interface for carrying both control and data in token format. A token decode circuit is positioned in certain of the stages for recognizing certain of the tokens as control tokens pertinent to that stage and for passing unrecognized control tokens along the pipeline. Reconfiguration processing circuits are positioned in selected stages and are responsive to a recognized control token for reconfiguring such stage to handle an identified DATA Token. A wide variety of unique supporting subsystem circuitry and processing techniques are disclosed for implementing the system, including memory addressing, transforming data using a common processing block, time synchronization, asynchronous swing buffering, storing of video information, a parallel Huffman decoder, and the like.

摘要翻译： 一种MPEG视频解压缩方法和装置，利用被布置为流水线处理机的两线接口互连的多个级。 控制令牌和数据令牌通过单个双线接口，以承载格式携带控制和数据。 令牌解码电路位于某些阶段，用于将某些令牌识别为与该级相关的控制令牌，并沿着管道传递未被识别的控制令牌。 重新配置处理电路定位在选定的阶段，并且响应于识别的控制令牌，以重新配置这样的阶段来处理所识别的数据令牌。 公开了各种独特的支持子系统电路和处理技术，用于实现系统，包括存储器寻址，使用公共处理块变换数据，时间同步，异步摆动缓冲，存储视频信息，并行霍夫曼解码器等 。

公开(公告)号：US06417859B1

公开(公告)日：2002-07-09

申请号：US09323627

申请日：1999-06-01

申请人： Martin W. Sotheran ,  Helen Rosemary Finch

发明人： Martin W. Sotheran ,  Helen Rosemary Finch

IPC分类号： G09G500

CPC分类号： G06F12/0207 ,  G06F12/04 ,  G06F12/0607 ,  G06F13/16 ,  G06F13/28 ,  H04N19/423 ,  H04N19/61

摘要： This invention provides a method to control the buffering of encoded video data organized as frames or fields. This method involves determining the picture number of each incoming decoded frame, determining the expected presentation number at any time and marking any buffer as ready when its picture number is on or after the presentation number.

摘要翻译： 本发明提供一种控制被组织为帧或场的编码视频数据的缓冲的方法。 该方法包括确定每个输入的解码帧的图像号码，在任何时间确定预期的呈现号码，并且当其图像号码在呈现号码之后或之后将任何缓冲器标记为就绪。

公开(公告)号：US5984512A

公开(公告)日：1999-11-16

申请号：US488348

申请日：1995-06-07

申请人： Anthony Mark Jones ,  Colin Smith ,  Helen Rosemary Finch ,  Anthony Peter John Claydon ,  Donald William Patterson ,  William P. Robbins ,  Nicholas Birch ,  David Andrew Barnes

发明人： Anthony Mark Jones ,  Colin Smith ,  Helen Rosemary Finch ,  Anthony Peter John Claydon ,  Donald William Patterson ,  William P. Robbins ,  Nicholas Birch ,  David Andrew Barnes

IPC分类号： H04N5/92 ,  G06F3/14 ,  G06F12/00 ,  G06F12/02 ,  G06F12/04 ,  G06F12/06 ,  G06F12/08 ,  G06F13/00 ,  G06F13/16 ,  G06F13/28 ,  G06F13/37 ,  G06T9/00 ,  G11B7/00 ,  G11B27/10 ,  H03M7/30 ,  H03M7/40 ,  H03M7/42 ,  H04L7/00 ,  H04L7/08 ,  H04L12/433 ,  H04N7/26 ,  H04N7/32 ,  H04N7/50 ,  H04N7/52 ,  G06F17/00

CPC分类号： H04N21/4307 ,  G06F12/0207 ,  G06F13/16 ,  G06F13/28 ,  H04N19/42 ,  H04N19/423 ,  H04N19/61 ,  H04N21/4305 ,  H04N21/44004 ,  G06F12/04 ,  H04N19/13 ,  H04N19/91

摘要： An MPEG video decompression method and apparatus utilizing a plurality of stages interconnected by a two-wire interface arranged as a pipeline processing machine. Control tokens and DATA Tokens pass over the single two-wire interface for carrying both control and in token format. A token decode circuit is positioned in certain of the stages for recognizing certain of the tokens as control tokens pertinent to that stage and for passing unrecognized control tokens along the pipeline. Reconfiguration processing circuits are positioned in select stages and are responsive to a recognized control token for reconfiguring such stages to handle an identified DATA Token. A wide variety of unique supporting subsystems circuitry and processing techniques are disclosed for implementing the system, including memory addressing, transforming data using a common processing block, time synchronization, asynchronous swing buffering, storing of video information, a parallel Huffman decoder, and the like.

摘要翻译： 一种MPEG视频解压缩方法和装置，利用被布置为流水线处理机的两线接口互连的多个级。 控制令牌和数据令牌通过单个双线接口，用于携带控制和令牌格式。 令牌解码电路位于某些阶段，用于将某些令牌识别为与该级相关的控制令牌，并沿着管道传递未被识别的控制令牌。 重新配置处理电路位于选择阶段，并响应于识别的控制令牌，以重新配置这些阶段来处理所识别的数据令牌。 公开了各种独特的支持子系统电路和处理技术，用于实现系统，包括存储器寻址，使用公共处理块变换数据，时间同步，异步摆动缓冲，存储视频信息，并行霍夫曼解码器等 。

公开(公告)号：US5835792A

公开(公告)日：1998-11-10

申请号：US487134

申请日：1995-06-07

申请人： Adrian P. Wise ,  Kevin D. Dewar ,  Anthony Mark Jones ,  Martin William Sotheran ,  Colin Smith ,  Helen Rosemary Finch ,  Anthony Peter John Claydon ,  Donald William Patterson ,  Mark Barnes ,  Andrew Peter Kuligowski ,  William P. Robbins ,  Nicholas Birch ,  David Andrew Barnes

发明人： Adrian P. Wise ,  Kevin D. Dewar ,  Anthony Mark Jones ,  Martin William Sotheran ,  Colin Smith ,  Helen Rosemary Finch ,  Anthony Peter John Claydon ,  Donald William Patterson ,  Mark Barnes ,  Andrew Peter Kuligowski ,  William P. Robbins ,  Nicholas Birch ,  David Andrew Barnes

IPC分类号： H04N5/92 ,  G06F3/14 ,  G06F12/00 ,  G06F12/02 ,  G06F12/04 ,  G06F12/06 ,  G06F12/08 ,  G06F13/00 ,  G06F13/16 ,  G06F13/28 ,  G06F13/37 ,  G06T9/00 ,  G11B7/00 ,  G11B27/10 ,  H03M7/30 ,  H03M7/40 ,  H03M7/42 ,  H04L7/00 ,  H04L7/08 ,  H04L12/433 ,  H04N7/26 ,  H04N7/32 ,  H04N7/50 ,  H04N7/52

CPC分类号： H04N21/4307 ,  G06F12/0207 ,  G06F13/16 ,  G06F13/28 ,  H04N19/42 ,  H04N19/423 ,  H04N19/61 ,  H04N21/4305 ,  H04N21/44004 ,  G06F12/04 ,  H04N19/13 ,  H04N19/91

摘要： An MPEG video decompression method and apparatus utilizing a plurality of stages interconnected by a two-wire interface arranged as a pipeline processing machine. Control tokens and DATA Tokens pass over the single two-wire interface for carrying both control and data in token format. A token decode circuit is positioned in certain of the stages for recognizing certain of the tokens as control tokens pertinent to that stage and for passing unrecognized control tokens along the pipeline. Reconfiguration processing circuits are positioned in selected stages and are responsive to a recognized control token for reconfiguring such stage to handle an identified DATA Token. A wide variety of unique supporting subsystem circuitry and processing techniques are disclosed for implementing the system, including memory addressing, transforming data using a common processing block, time synchronization, asynchronous swing buffering, storing of video information, a parallel Huffman decoder, and the like.

公开(公告)号：US5829007A

公开(公告)日：1998-10-27

申请号：US486908

申请日：1995-06-07

申请人： Adrian P. Wise ,  Kevin D. Dewar ,  Anthony Mark Jones ,  Martin William Sotheran ,  Colin Smith ,  Helen Rosemary Finch ,  Anthony Peter John Claydon ,  Donald William Patterson ,  Mark Barnes ,  Andrew Peter Kuligowski ,  William P. Robbins ,  Nicholas Birch ,  David Andrew Barnes

发明人： Adrian P. Wise ,  Kevin D. Dewar ,  Anthony Mark Jones ,  Martin William Sotheran ,  Colin Smith ,  Helen Rosemary Finch ,  Anthony Peter John Claydon ,  Donald William Patterson ,  Mark Barnes ,  Andrew Peter Kuligowski ,  William P. Robbins ,  Nicholas Birch ,  David Andrew Barnes

IPC分类号： H04N5/92 ,  G06F3/14 ,  G06F12/00 ,  G06F12/02 ,  G06F12/04 ,  G06F12/06 ,  G06F12/08 ,  G06F13/00 ,  G06F13/16 ,  G06F13/28 ,  G06F13/37 ,  G06T9/00 ,  G11B7/00 ,  G11B27/10 ,  H03M7/30 ,  H03M7/40 ,  H03M7/42 ,  H04L7/00 ,  H04L7/08 ,  H04L12/433 ,  H04N7/26 ,  H04N7/32 ,  H04N7/50 ,  H04N7/52

CPC分类号： H04N21/4307 ,  G06F12/0207 ,  G06F13/16 ,  G06F13/28 ,  H04N19/42 ,  H04N19/423 ,  H04N19/61 ,  H04N21/4305 ,  H04N21/44004 ,  G06F12/04 ,  H04N19/13 ,  H04N19/91

摘要： A RAM implementation of asynchronous swing buffering is provided in which two buffers are operated asynchronously; one is written while the other is read. Accordingly, this allows for a data stream having a fast rate of through-put to be resynchronized to another rate, while still maintaining a desired rate. In the invention, the write control and read control both have state indicators for communicating which buffer they are using and whether the controls are waiting for access or are, in fact, accessing that buffer.

摘要翻译： 提供了异步摆动缓冲的RAM实现，其中两个缓冲器是异步操作的; 一个是写在另一个被读取。 因此，这允许具有快速吞吐速率的数据流与另一个速率重新同步，同时仍然保持期望的速率。 在本发明中，写入控制和读取控制都具有用于通信它们正在使用哪个缓冲器的状态指示符，以及控制是否正在等待访问，或实际上访问该缓冲器。