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1.发明授权公开(公告)号：US07325184B2
公开(公告)日：2008-01-29
申请号：US11022811
申请日：2004-12-28
IPC分类号： H03M13/03
CPC分类号： H03M13/6502 , H03M13/3961 , H03M13/4107 , H03M13/4169 , H03M13/6561 , H03M13/6563 , H03M13/6569
摘要： A digital signal processor includes a functional unit configured to execute instructions. The functional unit determines a first minimum data of a first data and a second data, in parallel with a determination of a second minimum data of a third data and a fourth data. The functional unit outputs processed data including the first minimum data and the second minimum data. Each bit length of the first minimum data and the second minimum data is equal to n bits in length. A bit length of the processed data is equal to 2 n bits in length.
摘要翻译： 数字信号处理器包括被配置为执行指令的功能单元。 功能单元与第三数据和第四数据的第二最小数据的确定并行地确定第一数据和第二数据的第一最小数据。 功能单元输出包括第一最小数据和第二最小数据的处理数据。 第一最小数据和第二最小数据的每个位长度等于n位长度。 处理后的数据的位长度等于2 n位长。
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公开(公告)号：US06477661B2
公开(公告)日：2002-11-05
申请号：US09974807
申请日：2001-10-12
IPC分类号： G06F1100
CPC分类号： H03M13/6502 , H03M13/3961 , H03M13/4107 , H03M13/4169 , H03M13/6561 , H03M13/6563 , H03M13/6569
摘要： A method of operating a digital signal processor is provided. The digital signal processor may be provided as a radio communication mobile station, a radio communication base station apparatus, or a CDMA radio communication system. Each path metric PM1 and PM0 of an old state is added to each branch metric BM1 and BM0 separately. A path metric of a new state N is formed by comparing the value of PM1+BM1 to the value of PM0+BM0. A path metric of a new state N+2k−2 is formed by comparing the value of PM1+BM0 to PM0+BM1.
摘要翻译： 提供了一种操作数字信号处理器的方法。 数字信号处理器可以被提供为无线电通信移动台，无线电通信基站装置或CDMA无线电通信系统。 将旧状态的每个路径度量PM1和PM0分别添加到每个分支量度BM1和BM0。 通过将PM1 + BM1的值与PM0 + BM0的值进行比较来形成新状态N的路径度量。 通过将PM1 + BM0的值与PM0 + BM1进行比较来形成新状态N + 2k-2的路径度量。
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公开(公告)号：US07139968B2
公开(公告)日：2006-11-21
申请号：US10748242
申请日：2003-12-31
IPC分类号： H03M13/03
CPC分类号： H03M13/6502 , H03M13/3961 , H03M13/4107 , H03M13/4169 , H03M13/6561 , H03M13/6563 , H03M13/6569
摘要： A digital signal processor configured to perform a Viterbi algorithm includes an instruction fetching unit that fetches instructions and a decoding unit that decodes the instructions fetched by the instruction fetching unit. The digital signal processor also includes an execution unit that executes the instructions decoded by the decoding unit. The execution unit includes an arithmetic logic unit configured to perform a register—register arithmetic logic operation. The arithmetic logic unit compares a first data with a second data, in parallel with a comparison of a third data with a fourth data, and the execution unit outputs new path metrics. Each of the first data, the second data, the third data, and the fourth data is one of four results obtained by adding one of two path metrics to one of two branch metrics.
摘要翻译： 被配置为执行维特比算法的数字信号处理器包括取指令的指令取出单元和对由指令取出单元取出的指令进行解码的解码单元。 数字信号处理器还包括执行由解码单元解码的指令的执行单元。 执行单元包括被配置为执行寄存器寄存器算术逻辑运算的算术逻辑单元。 算术逻辑单元与第三数据与第四数据的比较并行地将第一数据与第二数据进行比较，并且执行单元输出新的路径度量。 第一数据，第二数据，第三数据和第四数据中的每一个是通过将两个路径度量中的一个添加到两个分支度量之一而获得的四个结果之一。
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公开(公告)号：US06330684B1
公开(公告)日：2001-12-11
申请号：US09147663
申请日：1999-02-09
IPC分类号： G06F1100
CPC分类号： H03M13/6502 , H03M13/3961 , H03M13/4107 , H03M13/4169 , H03M13/6561 , H03M13/6563 , H03M13/6569
摘要： Two path metrics (PM0, PM1) are read from path metric storing means 1, and two path metrics (BM0, BM1) are read from branch metric storing means 3. An ACS operation is executed using PM0+MB0 and PM1+BM1 by comparing means 5, adding means 6, comparison result storing means 7, and selecting means 8. In parallel with the ACS operation, an ACS operation is executed using PM0+MB1 and PM1+BM0 by comparing means 9, adding means 10, comparison result storing means 11, and selecting means 12.
摘要翻译： 从路径量度存储装置1读取两个路径度量（PM0，PM1），并从分支度量存储装置3读取两个路径度量（BM0，BM1）。通过比较使用PM0 + MB0和PM1 + BM1执行ACS操作 装置5，加法装置6，比较结果存储装置7和选择装置8.与ACS操作并行地，通过比较装置9，加法装置10，使用PM0 + MB1和PM1 + BM0执行ACS操作，比较结果存储 装置11和选择装置12。
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