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1.发明授权公开(公告)号：US07325184B2
公开(公告)日：2008-01-29
申请号：US11022811
申请日：2004-12-28
IPC分类号： H03M13/03
CPC分类号： H03M13/6502 , H03M13/3961 , H03M13/4107 , H03M13/4169 , H03M13/6561 , H03M13/6563 , H03M13/6569
摘要： A digital signal processor includes a functional unit configured to execute instructions. The functional unit determines a first minimum data of a first data and a second data, in parallel with a determination of a second minimum data of a third data and a fourth data. The functional unit outputs processed data including the first minimum data and the second minimum data. Each bit length of the first minimum data and the second minimum data is equal to n bits in length. A bit length of the processed data is equal to 2 n bits in length.
摘要翻译： 数字信号处理器包括被配置为执行指令的功能单元。 功能单元与第三数据和第四数据的第二最小数据的确定并行地确定第一数据和第二数据的第一最小数据。 功能单元输出包括第一最小数据和第二最小数据的处理数据。 第一最小数据和第二最小数据的每个位长度等于n位长度。 处理后的数据的位长度等于2 n位长。
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公开(公告)号：US06330684B1
公开(公告)日：2001-12-11
申请号：US09147663
申请日：1999-02-09
IPC分类号： G06F1100
CPC分类号： H03M13/6502 , H03M13/3961 , H03M13/4107 , H03M13/4169 , H03M13/6561 , H03M13/6563 , H03M13/6569
摘要： Two path metrics (PM0, PM1) are read from path metric storing means 1, and two path metrics (BM0, BM1) are read from branch metric storing means 3. An ACS operation is executed using PM0+MB0 and PM1+BM1 by comparing means 5, adding means 6, comparison result storing means 7, and selecting means 8. In parallel with the ACS operation, an ACS operation is executed using PM0+MB1 and PM1+BM0 by comparing means 9, adding means 10, comparison result storing means 11, and selecting means 12.
摘要翻译： 从路径量度存储装置1读取两个路径度量（PM0，PM1），并从分支度量存储装置3读取两个路径度量（BM0，BM1）。通过比较使用PM0 + MB0和PM1 + BM1执行ACS操作 装置5，加法装置6，比较结果存储装置7和选择装置8.与ACS操作并行地，通过比较装置9，加法装置10，使用PM0 + MB1和PM1 + BM0执行ACS操作，比较结果存储 装置11和选择装置12。
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公开(公告)号：US07139968B2
公开(公告)日：2006-11-21
申请号：US10748242
申请日：2003-12-31
IPC分类号： H03M13/03
CPC分类号： H03M13/6502 , H03M13/3961 , H03M13/4107 , H03M13/4169 , H03M13/6561 , H03M13/6563 , H03M13/6569
摘要： A digital signal processor configured to perform a Viterbi algorithm includes an instruction fetching unit that fetches instructions and a decoding unit that decodes the instructions fetched by the instruction fetching unit. The digital signal processor also includes an execution unit that executes the instructions decoded by the decoding unit. The execution unit includes an arithmetic logic unit configured to perform a register—register arithmetic logic operation. The arithmetic logic unit compares a first data with a second data, in parallel with a comparison of a third data with a fourth data, and the execution unit outputs new path metrics. Each of the first data, the second data, the third data, and the fourth data is one of four results obtained by adding one of two path metrics to one of two branch metrics.
摘要翻译： 被配置为执行维特比算法的数字信号处理器包括取指令的指令取出单元和对由指令取出单元取出的指令进行解码的解码单元。 数字信号处理器还包括执行由解码单元解码的指令的执行单元。 执行单元包括被配置为执行寄存器寄存器算术逻辑运算的算术逻辑单元。 算术逻辑单元与第三数据与第四数据的比较并行地将第一数据与第二数据进行比较，并且执行单元输出新的路径度量。 第一数据，第二数据，第三数据和第四数据中的每一个是通过将两个路径度量中的一个添加到两个分支度量之一而获得的四个结果之一。
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公开(公告)号：US06477661B2
公开(公告)日：2002-11-05
申请号：US09974807
申请日：2001-10-12
IPC分类号： G06F1100
CPC分类号： H03M13/6502 , H03M13/3961 , H03M13/4107 , H03M13/4169 , H03M13/6561 , H03M13/6563 , H03M13/6569
摘要： A method of operating a digital signal processor is provided. The digital signal processor may be provided as a radio communication mobile station, a radio communication base station apparatus, or a CDMA radio communication system. Each path metric PM1 and PM0 of an old state is added to each branch metric BM1 and BM0 separately. A path metric of a new state N is formed by comparing the value of PM1+BM1 to the value of PM0+BM0. A path metric of a new state N+2k−2 is formed by comparing the value of PM1+BM0 to PM0+BM1.
摘要翻译： 提供了一种操作数字信号处理器的方法。 数字信号处理器可以被提供为无线电通信移动台，无线电通信基站装置或CDMA无线电通信系统。 将旧状态的每个路径度量PM1和PM0分别添加到每个分支量度BM1和BM0。 通过将PM1 + BM1的值与PM0 + BM0的值进行比较来形成新状态N的路径度量。 通过将PM1 + BM0的值与PM0 + BM1进行比较来形成新状态N + 2k-2的路径度量。
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公开(公告)号：US06735714B2
公开(公告)日：2004-05-11
申请号：US10252394
申请日：2002-09-24
IPC分类号： G06F1100
CPC分类号： H03M13/6502 , H03M13/3961 , H03M13/4107 , H03M13/4169 , H03M13/6561 , H03M13/6563 , H03M13/6569
摘要： A digital signal processor capable of performing a Viterbi algorithm is provided. The digital signal processor includes an instruction fetching unit that fetches instructions; a decoding unit that decodes the instructions fetched by the instruction fetching unit, and an execution unit that executes the instructions decoded by the decoding unit. The execution unit includes a first comparing unit that compares first data with second data and a second comparing unit that compares third data with fourth data. The first comparing unit and the second comparing unit operate in parallel. Also, the first data, the second data, the third data, and the fourth data can each be one of four results obtained by adding one of two path metrics to one of two branch metrics. The execution unit outputs any two new path metrics in a high order position and a low order position respectively.
摘要翻译： 提供能够执行维特比算法的数字信号处理器。 数字信号处理器包括取指令的指令取出单元; 对由指令取出单元取出的指令进行解码的解码单元，以及执行由解码单元解码的指令的执行单元。 执行单元包括将第一数据与第二数据进行比较的第一比较单元和将第三数据与第四数据进行比较的第二比较单元。 第一比较单元和第二比较单元并行操作。 此外，第一数据，第二数据，第三数据和第四数据可以分别是通过将两个路径度量中的一个添加到两个分支度量之一而获得的四个结果之一。 执行单元分别在高阶位置和低位置输出任何两个新的路径度量。
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公开(公告)号：US20050163233A1
公开(公告)日：2005-07-28
申请号：US11022811
申请日：2004-12-28
CPC分类号： H03M13/6502 , H03M13/3961 , H03M13/4107 , H03M13/4169 , H03M13/6561 , H03M13/6563 , H03M13/6569
摘要： A digital signal processor includes a functional unit configured to execute instructions. The functional unit determines a first minimum data of a first data and a second data, in parallel with a determination of a second minimum data of a third data and a fourth data. The functional unit outputs processed data including the first minimum data and the second minimum data. Each bit length of the first minimum data and the second minimum data is equal to n bits in length. A bit length of the processed data is equal to 2n bits in length.
摘要翻译： 数字信号处理器包括被配置为执行指令的功能单元。 功能单元与第三数据和第四数据的第二最小数据的确定并行地确定第一数据和第二数据的第一最小数据。 功能单元输出包括第一最小数据和第二最小数据的处理数据。 第一最小数据和第二最小数据的每个位长度等于n位长度。 处理数据的位长度等于2n位长。
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公开(公告)号：US06233597B1
公开(公告)日：2001-05-15
申请号：US09110966
申请日：1998-07-07
IPC分类号： G06F1752
CPC分类号： G06F7/5324 , G06F7/49936 , G06F7/49994 , G06F7/5338
摘要： In a binary fixed-point number system in which the most significant bit is a sign bit and the decimal point is between the most significant bit and a bit which is lower by one bit than the most significant bit, the circuit scale for digit place aligning means is reduced and a double-precision multiplication with an excellent efficiency is realized. Products of the high-order word/low-order word of a double-precision multiplicand and the high-order word/low-order word of a double-precision multiplier are obtained by using a single-precision multiplying device. A digit place alignment addition operation is performed on the obtained products to produce a double-precision multiplication result. In this case, at least two digits are set before the decimal point, thereby allowing each of the products of the high-order word/low-order word of the double-precision multiplicand and the high-order word/low-order word of the double-precision multiplier, to be obtained at a bit width which is larger by at least one bit than a bit width of double precision.
摘要翻译： 在其中最高有效位是符号位的二进制定点数系统中，小数点位于最高有效位和比最高有效位低一位的位之间，数字位置对准的电路规模 减少了装置，实现了高效率的双精度乘法。 通过使用单精度乘法器获得双精度乘法器的高位字/低位字和双精度乘法器的高位字/低位字的乘积。 对获得的产品执行数字位置对准加法运算，以产生双精度乘法运算结果。 在这种情况下，在小数点之前设置至少两位数，从而允许双精度被乘数的高位字/低位字的每个乘积和高精度被乘数的高位字/低位字的乘积 双精度乘法器将以比双精度的位宽大至少一位的位宽度获得。
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公开(公告)号：US06334135B2
公开(公告)日：2001-12-25
申请号：US09811700
申请日：2001-03-20
申请人： Hideyuki Kabuo
发明人： Hideyuki Kabuo
IPC分类号： G06F1500
CPC分类号： G06F7/57 , G06F7/4991 , G06F7/49921 , G06F9/3001 , G06F9/30094 , G06F9/30105 , G06F9/3865
摘要： A plurality of units identified by respective addresses are disposed in a register file. Each of the units has a data register for storing data representative of a result of an arithmetic operation, a register for storing an overflow flag indicating the presence or absence of an occurrence of overflow in the arithmetic operation, and a register for storing a sign flag providing an indication of which one of a positive and a negative saturation value should replace the arithmetic operation result in the presence of an occurrence of overflow in the arithmetic operation. Each of the flags is updated in response to a write signal concerning its corresponding register. If at the moment when a data register is fed a read signal, a corresponding overflow flag is set, then either a positive or a negative saturation value, whichever corresponds to the sign flag, is generated on the input side of an arithmetic unit.
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公开(公告)号：US06260136B1
公开(公告)日：2001-07-10
申请号：US09135487
申请日：1998-08-18
申请人： Hideyuki Kabuo
发明人： Hideyuki Kabuo
IPC分类号： G06F9302
CPC分类号： G06F9/3001 , G06F9/30101 , G06F9/30141
摘要： In addition to a register file having four general-purpose registers each for storing data, an arithmetic and logic unit for executing an addition instruction, a subtraction instruction, or the like, and a multiplier unit for executing a multiplication instruction, there are provided a controller and a substitute register for storing only data representing the result of operation performed by the multiplier unit in place of any of the four general-purpose registers in the register file. The controller controls the writing and reading of data in and from the register file and the writing and reading of data in and from the substitute register based on a multiplication tag indicative of the one of the four general-purpose registers in place of which the substitute register stores the data representing the result of multiplication and on a multiplication execute flag indicative of whether the data stored in the substitute register is effective or ineffective.
摘要翻译： 除了具有四个用于存储数据的通用寄存器的寄存器文件之外，还包括用于执行加法指令的算术和逻辑单元，减法指令等，以及用于执行乘法指令的乘法器单元， 控制器和替代寄存器，用于仅存储表示乘法器单元执行的操作结果的数据，代替寄存器文件中的四个通用寄存器中的任一个。 控制器控制在寄存器文件中写入和读取数据，以及根据指示四个通用寄存器之一的乘法标签代替替代寄存器中的数据的写入和读取，代替替换 寄存器存储表示乘法结果的数据，以及表示存储在替代寄存器中的数据是有效还是无效的乘法执行标志。
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公开(公告)号：US20110210748A1
公开(公告)日：2011-09-01
申请号：US13103753
申请日：2011-05-09
申请人： Ryota NISHIKAWA , Hideyuki Kabuo
发明人： Ryota NISHIKAWA , Hideyuki Kabuo
IPC分类号： G01R31/02
CPC分类号： G01R31/31715 , H01L27/088
摘要： A semiconductor integrated circuit and an electronic information device each of which can detect a fault at one of control signals of tristate gates with a smaller area than conventional ones and without reducing the speed of normal operation, by providing a fault detector using tristate gates.
摘要翻译： 一种半导体集成电路和电子信息装置，通过提供使用三态门的故障检测器，每一个可以以比传统门的区域小的三态门的控制信号中的一个检测故障，并且不降低正常操作的速度。
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