公开(公告)号：US20110201205A1

公开(公告)日：2011-08-18

申请号：US12879874

申请日：2010-09-10

申请人： Khalid M. Sirajuddin ,  Digvijay Raorane ,  Jon C. Farr ,  Sharma V. Pamarthy

发明人： Khalid M. Sirajuddin ,  Digvijay Raorane ,  Jon C. Farr ,  Sharma V. Pamarthy

IPC分类号： H01L21/302

CPC分类号： H01L21/76232 ,  H01L21/3086

摘要： Methods of forming deep trenches in substrates are described. A method includes providing a substrate with a patterned film disposed thereon, the patterned film including a trench having a first width and a pair of sidewalls, the trench exposing the top surface of the substrate. The method also includes forming a material layer over the patterned film and conformal with the trench. The method also includes etching the material layer to form sidewall spacers along the pair of sidewalls of the trench, the sidewall spacers reducing the first width of the trench to a second width. The method also includes etching the substrate to form a deep trench in the substrate, the deep trench undercutting at least a portion of the sidewall spacers.

摘要翻译： 描述了在衬底中形成深沟槽的方法。 一种方法包括提供其上设置有图案化膜的衬底，所述图案化膜包括具有第一宽度和一对侧壁的沟槽，所述沟槽暴露衬底的顶表面。 该方法还包括在图案化膜上形成材料层并与沟槽保形。 该方法还包括蚀刻材料层以沿着沟槽的一对侧壁形成侧壁间隔物，侧壁间隔物将沟槽的第一宽度减小到第二宽度。 该方法还包括蚀刻衬底以在衬底中形成深沟槽，深沟槽底切侧壁间隔物的至少一部分。

公开(公告)号：US08158522B2

公开(公告)日：2012-04-17

申请号：US12879874

申请日：2010-09-10

申请人： Khalid M. Sirajuddin ,  Digvijay Raorane ,  Jon C. Farr ,  Sharma V. Pamarthy

发明人： Khalid M. Sirajuddin ,  Digvijay Raorane ,  Jon C. Farr ,  Sharma V. Pamarthy

IPC分类号： H01L21/311

CPC分类号： H01L21/76232 ,  H01L21/3086

摘要： Methods of forming deep trenches in substrates are described. A method includes providing a substrate with a patterned film disposed thereon, the patterned film including a trench having a first width and a pair of sidewalls, the trench exposing the top surface of the substrate. The method also includes forming a material layer over the patterned film and conformal with the trench. The method also includes etching the material layer to form sidewall spacers along the pair of sidewalls of the trench, the sidewall spacers reducing the first width of the trench to a second width. The method also includes etching the substrate to form a deep trench in the substrate, the deep trench undercutting at least a portion of the sidewall spacers.

摘要翻译： 描述了在衬底中形成深沟槽的方法。 一种方法包括提供其上设置有图案化膜的衬底，所述图案化膜包括具有第一宽度和一对侧壁的沟槽，所述沟槽暴露衬底的顶表面。 该方法还包括在图案化膜上形成材料层并与沟槽保形。 该方法还包括蚀刻材料层以沿着沟槽的一对侧壁形成侧壁间隔物，侧壁间隔物将沟槽的第一宽度减小到第二宽度。 该方法还包括蚀刻衬底以在衬底中形成深沟槽，深沟槽底切侧壁间隔物的至少一部分。

公开(公告)号：US20110217832A1

公开(公告)日：2011-09-08

申请号：US12879924

申请日：2010-09-10

申请人： Digvijay Raorane ,  Khalid M. Sirajuddin ,  Jon C. Farr ,  Sharma V. Pamarthy

发明人： Digvijay Raorane ,  Khalid M. Sirajuddin ,  Jon C. Farr ,  Sharma V. Pamarthy

IPC分类号： H01L21/3205 ,  H01L21/283

CPC分类号： H01L21/31116 ,  H01L21/76831 ,  H01L21/76898

摘要： Methods of filling deep trenches in substrates are described. A method includes providing a substrate with a deep trench formed therein. The method also includes forming a dielectric layer conformal with the substrate and the deep trench. The method also includes, with the entire portion of the dielectric layer conformal with the deep trench exposed, removing at least a portion, but not all, of the dielectric layer at the top of the deep trench with a relatively low bias plasma etch process.

摘要翻译： 描述了在衬底中填充深沟槽的方法。 一种方法包括提供其中形成有深沟槽的衬底。 该方法还包括形成与衬底和深沟槽共形的电介质层。 该方法还包括，电介质层的整个部分与暴露的深沟槽保持一致，用相对低的偏压等离子体蚀刻工艺在深沟槽的顶部除去介电层的至少一部分但不是全部。

公开(公告)号：US09023227B2

公开(公告)日：2015-05-05

申请号：US13480967

申请日：2012-05-25

申请人： Jivko Dinev ,  Saravjeet Singh ,  Khalid M. Sirajuddin ,  Tong Liu ,  Puneet Bajaj ,  Rohit Mishra ,  Sonal A. Srivastava ,  Madhava Rao Yalamanchili ,  Ajay Kumar

发明人： Jivko Dinev ,  Saravjeet Singh ,  Khalid M. Sirajuddin ,  Tong Liu ,  Puneet Bajaj ,  Rohit Mishra ,  Sonal A. Srivastava ,  Madhava Rao Yalamanchili ,  Ajay Kumar

IPC分类号： B44C1/22 ,  H01L21/3065 ,  H01L21/768

CPC分类号： H01L21/30655 ,  H01L21/76898

摘要： Embodiments described herein generally relate to a substrate processing system and related methods, such as an etching/deposition method. The method comprises (A) depositing a protective layer on a first layer disposed on a substrate in an etch reactor, wherein a plasma source power of 4,500 Watts or greater is applied while depositing the protective layer, (B) etching the protective layer in the etch reactor, wherein the plasma source power of 4,500 Watts or greater is applied while etching the protective layer, and (C) etching the first layer in the etch reactor, wherein the plasma source power of 4,500 Watts or greater is applied while etching the first layer, wherein a time for the depositing a protective layer (A) comprises less than 30% of a total cycle time for the depositing a protective layer (A), the etching the protective layer (B), and the etching the first layer (C).

摘要翻译： 本文描述的实施例通常涉及衬底处理系统和相关方法，例如蚀刻/沉积方法。 该方法包括：（A）在蚀刻反应器中设置在衬底上的第一层上沉积保护层，其中在沉积保护层的同时施加4500瓦特或更大的等离子体源功率，（B）蚀刻保护层中的保护层 蚀刻反应器，其中施加4500瓦或更大的等离子体源功率，同时蚀刻保护层，和（C）蚀刻蚀刻反应器中的第一层，其中施加4500瓦特或更大的等离子体源功率，同时蚀刻第一 层，其中沉积保护层（A）的时间包括小于用于沉积保护层（A）的总循环时间的30％，蚀刻保护层（B）和蚀刻第一层（ C）。

公开(公告)号：US20130005152A1

公开(公告)日：2013-01-03

申请号：US13480967

申请日：2012-05-25

申请人： JIVKO DINEV ,  Saravjeet Singh ,  Khalid M. Sirajuddin ,  Tong Liu ,  Puneet Bajaj ,  Rohit Mishra ,  Sonal A. Srivastava ,  Madhava Rao Yalamanchili ,  Ajay Kumar

发明人： JIVKO DINEV ,  Saravjeet Singh ,  Khalid M. Sirajuddin ,  Tong Liu ,  Puneet Bajaj ,  Rohit Mishra ,  Sonal A. Srivastava ,  Madhava Rao Yalamanchili ,  Ajay Kumar

IPC分类号： H01L21/3065

CPC分类号： H01L21/30655 ,  H01L21/76898

摘要： Embodiments described herein generally relate to a substrate processing system and related methods, such as an etching/deposition method. The method comprises (A) depositing a protective layer on a first layer disposed on a substrate in an etch reactor, wherein a plasma source power of 4,500 Watts or greater is applied while depositing the protective layer, (B) etching the protective layer in the etch reactor, wherein the plasma source power of 4,500 Watts or greater is applied while etching the protective layer, and (C) etching the first layer in the etch reactor, wherein the plasma source power of 4,500 Watts or greater is applied while etching the first layer, wherein a time for the depositing a protective layer (A) comprises less than 30% of a total cycle time for the depositing a protective layer (A), the etching the protective layer (B), and the etching the first layer (C).

摘要翻译： 本文描述的实施例通常涉及衬底处理系统和相关方法，例如蚀刻/沉积方法。 该方法包括：（A）在蚀刻反应器中设置在衬底上的第一层上沉积保护层，其中在沉积保护层的同时施加4500瓦特或更大的等离子体源功率，（B）蚀刻保护层中的保护层 蚀刻反应器，其中施加4500瓦或更大的等离子体源功率，同时蚀刻保护层，和（C）蚀刻蚀刻反应器中的第一层，其中施加4500瓦特或更大的等离子体源功率，同时蚀刻第一 层，其中沉积保护层（A）的时间包括小于用于沉积保护层（A）的总循环时间的30％，蚀刻保护层（B）和蚀刻第一层（ C）。

公开(公告)号：US20130288474A1

公开(公告)日：2013-10-31

申请号：US13458172

申请日：2012-04-27

申请人： ROHIT MISHRA ,  JAYAGATAN R. VIJAYEN ,  KHALID M. SIRAJUDDIN ,  BRAD EATON ,  MADHAVA RAO YALAMANCHILI

发明人： ROHIT MISHRA ,  JAYAGATAN R. VIJAYEN ,  KHALID M. SIRAJUDDIN ,  BRAD EATON ,  MADHAVA RAO YALAMANCHILI

IPC分类号： H01L21/768

CPC分类号： H01L21/76808 ,  H01J37/32357

摘要： Methods for fabricating dual damascene interconnect structures are provided herein. In some embodiments, a method for fabricating a dual damascene interconnect structure may include etching a via into a substrate through a first photoresist layer; patterning a second photoresist layer atop the substrate to define a trench pattern, wherein the via is aligned within the trench pattern, and wherein a portion of undeveloped photoresist remains in the via after patterning; and etching the trench into the substrate to form a dual damascene pattern in the substrate.

摘要翻译： 本文提供了制造双镶嵌互连结构的方法。 在一些实施例中，制造双镶嵌互连结构的方法可以包括通过第一光致抗蚀剂层将通孔蚀刻到衬底中; 在衬底上方形成第二光致抗蚀剂层以限定沟槽图案，其中通孔在沟槽图案内对准，并且其中未图案化的光致抗蚀剂的一部分在图案化之后保留在通孔中; 并且将沟槽蚀刻到衬底中以在衬底中形成双镶嵌图案。