公开(公告)号：US08242819B2

公开(公告)日：2012-08-14

申请号：US13042244

申请日：2011-03-07

申请人： Seung Jun Bae ,  Kwang Il Park ,  Sam Young Bang ,  Gil Shin Moon ,  Ki Woong Yeom

发明人： Seung Jun Bae ,  Kwang Il Park ,  Sam Young Bang ,  Gil Shin Moon ,  Ki Woong Yeom

IPC分类号： H03L7/06

CPC分类号： H03L7/06 ,  G11C7/22 ,  G11C7/222 ,  G11C2207/2254

摘要： A method and apparatus for tuning a phase of a data clock signal having a different frequency than a main clock signal. The method of tuning includes coarse tuning by receiving the data clock signal, dividing the data clock signal to generate a frequency-divided clock signal having a same frequency as the main clock signal, repeatedly shifting the frequency-divided clock signal to generate multiphase frequency-divided clock signals at a predetermined phase interval, comparing a phase of each of the multiphase frequency-divided clock signals with a phase of the main clock signal, and determining a phase shift amount based on a comparison result, and fine tuning by comparing a phase of a multiphase frequency-divided clock signal corresponding to the phase shift amount with the phase of the main clock signal and adjusting the phase of the data clock signal by a predetermined phase step based on the comparison result.

摘要翻译： 一种用于调谐具有与主时钟信号不同的频率的数据时钟信号的相位的方法和装置。 调谐方法包括：通过接收数据时钟信号进行粗调，分割数据时钟信号以产生与主时钟信号具有相同频率的分频时钟信号，重新移位分频时钟信号以产生多相频率 - 以预定的相位间隔分配时钟信号，将多相分频时钟信号中的每一个的相位与主时钟信号的相位进行比较，并且基于比较结果确定相移量，并且通过比较相位 对应于与主时钟信号的相位的相移量相对应的多相分频时钟信号，并且基于比较结果调整数据时钟信号的相位预定相位步长。

公开(公告)号：US20090251181A1

公开(公告)日：2009-10-08

申请号：US12385431

申请日：2009-04-08

申请人： Seung Jun Bae ,  Kwang Il Park ,  Sam Young Bang ,  Gil Shin Moon ,  Ki Woong Yeom

发明人： Seung Jun Bae ,  Kwang Il Park ,  Sam Young Bang ,  Gil Shin Moon ,  Ki Woong Yeom

IPC分类号： H03L7/06

CPC分类号： H03L7/06 ,  G11C7/22 ,  G11C7/222 ,  G11C2207/2254

摘要： A method and apparatus for tuning a phase of a data clock signal having a different frequency than a main clock signal. The method of tuning includes coarse tuning by receiving the data clock signal, dividing the data clock signal to generate a frequency-divided clock signal having a same frequency as the main clock signal, repeatedly shifting the frequency-divided clock signal to generate multiphase frequency-divided clock signals at a predetermined phase interval, comparing a phase of each of the multiphase frequency-divided clock signals with a phase of the main clock signal, and determining a phase shift amount based on a comparison result, and fine tuning by comparing a phase of a multiphase frequency-divided clock signal corresponding to the phase shift amount with the phase of the main clock signal and adjusting the phase of the data clock signal by a predetermined phase step based on the comparison result.

摘要翻译： 一种用于调谐具有与主时钟信号不同的频率的数据时钟信号的相位的方法和装置。 调谐方法包括：通过接收数据时钟信号进行粗调，分割数据时钟信号以产生与主时钟信号具有相同频率的分频时钟信号，重新移位分频时钟信号以产生多相频率 - 以预定的相位间隔分配时钟信号，将多相分频时钟信号中的每一个的相位与主时钟信号的相位进行比较，并且基于比较结果确定相移量，并且通过比较相位 对应于与主时钟信号的相位的相移量相对应的多相分频时钟信号，并且基于比较结果调整数据时钟信号的相位预定相位步长。

公开(公告)号：US20140050020A1

公开(公告)日：2014-02-20

申请号：US13931275

申请日：2013-06-28

申请人： Jae-Young LEE ,  Bong-Jin KANG ,  Jung-Hwa HWANG ,  Ki-Woong YEOM ,  Young-Kwan KIM ,  Dong-Hyun SHON

发明人： Jae-Young LEE ,  Bong-Jin KANG ,  Jung-Hwa HWANG ,  Ki-Woong YEOM ,  Young-Kwan KIM ,  Dong-Hyun SHON

IPC分类号： G11C11/16

CPC分类号： G11C11/1653 ,  G11C7/1054 ,  G11C7/1081 ,  G11C11/161 ,  G11C11/1655 ,  G11C11/1657 ,  G11C11/1659 ,  G11C11/1673 ,  G11C11/1675

摘要： Provided is a semiconductor memory device including a column decoder, a plurality of sub-cell blocks, and a bit line selection circuit. The column decoder is configured to decode column addresses and drive column selection signals. Each of the sub-cell blocks includes a plurality of bit lines, a plurality of word lines, and a plurality of memory cells connected to the plurality of bit lines and the plurality of word lines. The bit line selection circuit includes a plurality of bit line connection controllers, and is configured to select one or more bit lines in response to the column selection signals. Each of the bit line connection controllers electrically couples a respective first bit line to corresponding first and second local input/output (I/O) lines in response to first and second column selection signals of the column selection signals, respectively.

摘要翻译： 提供了包括列解码器，多个子单元块和位线选择电路的半导体存储器件。 列解码器被配置为解码列地址并驱动列选择信号。 每个子单元块包括多个位线，多个字线和连接到多个位线和多个字线的多个存储单元。 位线选择电路包括多个位线连接控制器，并且被配置为响应于列选择信号选择一个或多个位线。 每个位线连接控制器分别响应于列选择信号的第一和第二列选择信号将相应的第一位线电耦合到相应的第一和第二本地输入/输出（I / O）线。

公开(公告)号：US20110158030A1

公开(公告)日：2011-06-30

申请号：US13042244

申请日：2011-03-07

申请人： Seung Jun BAE ,  Kwang Il Park ,  Sam Young Bang ,  Gil Shin Moon ,  Ki Woong Yeom

发明人： Seung Jun BAE ,  Kwang Il Park ,  Sam Young Bang ,  Gil Shin Moon ,  Ki Woong Yeom

IPC分类号： G11C8/00

CPC分类号： H03L7/06 ,  G11C7/22 ,  G11C7/222 ,  G11C2207/2254

摘要： A method and apparatus for tuning a phase of a data clock signal having a different frequency than a main clock signal. The method of tuning includes coarse tuning by receiving the data clock signal, dividing the data clock signal to generate a frequency-divided clock signal having a same frequency as the main clock signal, repeatedly shifting the frequency-divided clock signal to generate multiphase frequency-divided clock signals at a predetermined phase interval, comparing a phase of each of the multiphase frequency-divided clock signals with a phase of the main clock signal, and determining a phase shift amount based on a comparison result, and fine tuning by comparing a phase of a multiphase frequency-divided clock signal corresponding to the phase shift amount with the phase of the main clock signal and adjusting the phase of the data clock signal by a predetermined phase step based on the comparison result.

摘要翻译： 一种用于调谐具有与主时钟信号不同的频率的数据时钟信号的相位的方法和装置。 调谐方法包括：通过接收数据时钟信号进行粗调，分割数据时钟信号以产生与主时钟信号具有相同频率的分频时钟信号，重新移位分频时钟信号以产生多相频率 - 以预定的相位间隔分配时钟信号，将多相分频时钟信号中的每一个的相位与主时钟信号的相位进行比较，并且基于比较结果确定相移量，并且通过比较相位 对应于与主时钟信号的相位的相移量相对应的多相分频时钟信号，并且基于比较结果调整数据时钟信号的相位预定相位步长。

公开(公告)号：US07902887B2

公开(公告)日：2011-03-08

申请号：US12385431

申请日：2009-04-08

申请人： Seung Jun Bae ,  Kwang Il Park ,  Sam Young Bang ,  Gil Shin Moon ,  Ki Woong Yeom

发明人： Seung Jun Bae ,  Kwang Il Park ,  Sam Young Bang ,  Gil Shin Moon ,  Ki Woong Yeom

IPC分类号： H03L7/06

CPC分类号： H03L7/06 ,  G11C7/22 ,  G11C7/222 ,  G11C2207/2254

摘要： A method and apparatus for tuning a phase of a data clock signal having a different frequency than a main clock signal. The method of tuning includes coarse tuning by receiving the data clock signal, dividing the data clock signal to generate a frequency-divided clock signal having a same frequency as the main clock signal, repeatedly shifting the frequency-divided clock signal to generate multiphase frequency-divided clock signals at a predetermined phase interval, comparing a phase of each of the multiphase frequency-divided clock signals with a phase of the main clock signal, and determining a phase shift amount based on a comparison result, and fine tuning by comparing a phase of a multiphase frequency-divided clock signal corresponding to the phase shift amount with the phase of the main clock signal and adjusting the phase of the data clock signal by a predetermined phase step based on the comparison result.

摘要翻译： 一种用于调谐具有与主时钟信号不同的频率的数据时钟信号的相位的方法和装置。 调谐方法包括：通过接收数据时钟信号进行粗调，分割数据时钟信号以产生与主时钟信号具有相同频率的分频时钟信号，重新移位分频时钟信号以产生多相频率 - 以预定的相位间隔分配时钟信号，将多相分频时钟信号中的每一个的相位与主时钟信号的相位进行比较，并且基于比较结果确定相移量，并且通过比较相位 对应于与主时钟信号的相位的相移量相对应的多相分频时钟信号，并且基于比较结果调整数据时钟信号的相位预定相位步长。