公开(公告)号：US06680239B1

公开(公告)日：2004-01-20

申请号：US09624025

申请日：2000-07-24

申请人： Cher Liang Cha ,  Kok Keng Ong ,  Alex See ,  Lap Chan

发明人： Cher Liang Cha ,  Kok Keng Ong ,  Alex See ,  Lap Chan

IPC分类号： H01L2176

CPC分类号： H01L21/76237

摘要： A method for forming shallow trench isolation (STI) with a higher aspect ratio is given. This method allows the formation of narrower and deeper trench isolation regions while avoiding substrate damage due to excessive etching and severe microloading effects. In addition, it yields uniform depth trenches while avoiding problems of etch residue at the bottom of the trench. This method is achieved by using a process where a trench is etched, and an oxide layer grown along the bottom and sidewalls of the trench. Oxygen or field isolation ions are then implanted into the bottom of the trench. A nitride spacer is then formed along the bottom and sidewalls of the trench, followed by an isotropic etch removing the nitride and oxide from the bottom of the trench. An oxide deposition then fills the trench, followed by a planarization step completing the isolation structure.

摘要翻译： 给出了一种形成具有较高纵横比的浅沟槽隔离（STI）的方法。 该方法允许形成更窄和更深的沟槽隔离区域，同时避免由于过度蚀刻和严重的微负载效应引起的基板损伤。 此外，它产生均匀的深度沟槽，同时避免沟槽底部的蚀刻残留问题。 该方法通过使用其中蚀刻沟槽的工艺和沿着沟槽的底部和侧壁生长的氧化物层来实现。 然后将氧或场隔离离子注入到沟槽的底部。 然后沿着沟槽的底部和侧壁形成氮化物间隔物，随后通过各向同性蚀刻从沟槽的底部去除氮化物和氧化物。 氧化物沉积然后填充沟槽，随后是完成隔离结构的平坦化步骤。

公开(公告)号：US06268276B1

公开(公告)日：2001-07-31

申请号：US09216823

申请日：1998-12-21

申请人： Lap Chan ,  Kheng Chok Tee ,  Kok Keng Ong ,  Chin Hwee Seah

发明人： Lap Chan ,  Kheng Chok Tee ,  Kok Keng Ong ,  Chin Hwee Seah

IPC分类号： H01L214763

CPC分类号： H01L21/7682

摘要： A new method of forming air gaps between adjacent conducting lines of a semiconductor circuit by using a “holes everywhere” or a “reverse metal holes” mask that can be used to create holes in a dielectric layer. The dielectric that is being etched has been deposited across conducting lines, the holes that are being formed in this manner are closed by depositing a dielectric across the top of the holes. The holes can be etched across the entire layer of the deposited dielectric or can be etched in between the conducting lines.

摘要翻译： 在半导体电路的相邻导线之间通过使用“各处的孔”形成气隙的新方法或可用于在电介质层中产生孔的“反向金属孔”掩模。 被蚀刻的电介质已经沉积在导电线之间，以这种方式形成的孔通过在孔的顶部沉积电介质来封闭。 可以在沉积的电介质的整个层上蚀刻孔，或者可以在导电线之间蚀刻孔。

公开(公告)号：US06251798B1

公开(公告)日：2001-06-26

申请号：US09359894

申请日：1999-07-26

申请人： Choi Pheng Soo ,  Kheng Chok Tee ,  Kok Keng Ong ,  Lap Chan

发明人： Choi Pheng Soo ,  Kheng Chok Tee ,  Kok Keng Ong ,  Lap Chan

IPC分类号： H01L2131

CPC分类号： H01L21/7682 ,  H01L23/5222 ,  H01L2924/0002 ,  H01L2924/00

摘要： A method for the formation of an air gap structure for use in inter-metal applications. A metal pattern of metal lines is formed, a layer of Plasma Polymerized Methylsilane (PPMS) resist is deposited on top of this pattern. The surface of the PPMS resist is subjected to selective exposure. The unexposed PPMS is removed after which the process is completed by closing up the openings within the PPMS.

摘要翻译： 一种用于形成用于金属间应用的气隙结构的方法。 形成金属线的金属图案，在该图案的顶部上沉积一层等离子聚合甲基硅烷（PPMS）抗蚀剂。 对PPMS抗蚀剂的表面进行选择性曝光。 未曝光的PPMS被去除，之后通过关闭PPMS内的开口来完成该过程。

公开(公告)号：US6150232A

公开(公告)日：2000-11-21

申请号：US244877

申请日：1999-02-05

申请人： Lap Chan ,  Cher Liang Cha ,  Kok Keng Ong ,  Kheng Chok Tee

发明人： Lap Chan ,  Cher Liang Cha ,  Kok Keng Ong ,  Kheng Chok Tee

IPC分类号： H01L21/312 ,  H01L21/316 ,  H01L21/768 ,  H01L21/76

CPC分类号： H01L21/7682 ,  H01L21/3124 ,  H01L21/31612

摘要： A method for creating low intra-level dielectric interface between conducting lines using conventional deposition and etching processes. A layer of conducting lines is formed interspersed with dielectric material. A dummy, high-density pattern of low k dielectric material is created on top of this layer. The dielectric material between the metal lines is removed. The dummy high-density pattern is interconnected, deposited on top of this interconnected layer is a low k dielectric to form an inter layer dielectric.

摘要翻译： 一种使用常规沉积和蚀刻工艺在导线之间产生低内部电介质界面的方法。 一层导电线形成为散布有电介质材料。 在该层的顶部上形成低k电介质材料的虚拟高密度图案。 去除金属线之间的电介质材料。 虚拟高密度图案是互连的，沉积在该互连层的顶部上的是低k电介质以形成层间电介质。