公开(公告)号：US06251798B1

公开(公告)日：2001-06-26

申请号：US09359894

申请日：1999-07-26

申请人： Choi Pheng Soo ,  Kheng Chok Tee ,  Kok Keng Ong ,  Lap Chan

发明人： Choi Pheng Soo ,  Kheng Chok Tee ,  Kok Keng Ong ,  Lap Chan

IPC分类号： H01L2131

CPC分类号： H01L21/7682 ,  H01L23/5222 ,  H01L2924/0002 ,  H01L2924/00

摘要： A method for the formation of an air gap structure for use in inter-metal applications. A metal pattern of metal lines is formed, a layer of Plasma Polymerized Methylsilane (PPMS) resist is deposited on top of this pattern. The surface of the PPMS resist is subjected to selective exposure. The unexposed PPMS is removed after which the process is completed by closing up the openings within the PPMS.

摘要翻译： 一种用于形成用于金属间应用的气隙结构的方法。 形成金属线的金属图案，在该图案的顶部上沉积一层等离子聚合甲基硅烷（PPMS）抗蚀剂。 对PPMS抗蚀剂的表面进行选择性曝光。 未曝光的PPMS被去除，之后通过关闭PPMS内的开口来完成该过程。

公开(公告)号：US06268276B1

公开(公告)日：2001-07-31

申请号：US09216823

申请日：1998-12-21

申请人： Lap Chan ,  Kheng Chok Tee ,  Kok Keng Ong ,  Chin Hwee Seah

发明人： Lap Chan ,  Kheng Chok Tee ,  Kok Keng Ong ,  Chin Hwee Seah

IPC分类号： H01L214763

CPC分类号： H01L21/7682

摘要： A new method of forming air gaps between adjacent conducting lines of a semiconductor circuit by using a “holes everywhere” or a “reverse metal holes” mask that can be used to create holes in a dielectric layer. The dielectric that is being etched has been deposited across conducting lines, the holes that are being formed in this manner are closed by depositing a dielectric across the top of the holes. The holes can be etched across the entire layer of the deposited dielectric or can be etched in between the conducting lines.

摘要翻译： 在半导体电路的相邻导线之间通过使用“各处的孔”形成气隙的新方法或可用于在电介质层中产生孔的“反向金属孔”掩模。 被蚀刻的电介质已经沉积在导电线之间，以这种方式形成的孔通过在孔的顶部沉积电介质来封闭。 可以在沉积的电介质的整个层上蚀刻孔，或者可以在导电线之间蚀刻孔。

公开(公告)号：US6150232A

公开(公告)日：2000-11-21

申请号：US244877

申请日：1999-02-05

申请人： Lap Chan ,  Cher Liang Cha ,  Kok Keng Ong ,  Kheng Chok Tee

发明人： Lap Chan ,  Cher Liang Cha ,  Kok Keng Ong ,  Kheng Chok Tee

IPC分类号： H01L21/312 ,  H01L21/316 ,  H01L21/768 ,  H01L21/76

CPC分类号： H01L21/7682 ,  H01L21/3124 ,  H01L21/31612

摘要： A method for creating low intra-level dielectric interface between conducting lines using conventional deposition and etching processes. A layer of conducting lines is formed interspersed with dielectric material. A dummy, high-density pattern of low k dielectric material is created on top of this layer. The dielectric material between the metal lines is removed. The dummy high-density pattern is interconnected, deposited on top of this interconnected layer is a low k dielectric to form an inter layer dielectric.

摘要翻译： 一种使用常规沉积和蚀刻工艺在导线之间产生低内部电介质界面的方法。 一层导电线形成为散布有电介质材料。 在该层的顶部上形成低k电介质材料的虚拟高密度图案。 去除金属线之间的电介质材料。 虚拟高密度图案是互连的，沉积在该互连层的顶部上的是低k电介质以形成层间电介质。

公开(公告)号：US06468906B1

公开(公告)日：2002-10-22

申请号：US09617009

申请日：2000-07-14

申请人： Lap Chan ,  Kuan Pei Yap ,  Kheng Chok Tee ,  Flora S. Ip ,  Wye Boon Loh

发明人： Lap Chan ,  Kuan Pei Yap ,  Kheng Chok Tee ,  Flora S. Ip ,  Wye Boon Loh

IPC分类号： H01L2144

CPC分类号： H01L21/76849 ,  H01L21/76858 ,  H01L21/76867 ,  H01L21/76886

摘要： An interconnect line on an IMD layer on a semiconductor device is formed in an interconnect hole in the IMD layer. The interconnect hole has walls and a bottom in the IMD layer. A diffusion barrier is formed on the walls and the bottom of the hole. Fill the interconnect hole with a copper metal line. Perform a CMP step to planarize the device and to remove copper above the IMD layer. Deposit a passivating metal layer on the surface of the copper metal line encapsulating the copper metal line at the top of the hole. Alternatively, a blanket deposit of a copper metal line layer covers the diffusion layer and fills the interconnect hole with a copper metal line. Perform a CMP process to planarize the device to remove copper above the IMD layer. Deposit a passivating metal layer on the surface of the copper metal line encapsulating the copper metal line at the top of the hole in a self-aligned deposition process.

摘要翻译： 在IMD层中的互连孔中形成半导体器件上的IMD层上的互连线。 互连孔在IMD层中具有壁和底部。 在孔的壁和底部形成扩散阻挡层。 用铜金属线填充互连孔。 执行CMP步骤以使器件平坦化，并移除IMD层上方的铜。 在孔的顶部包埋铜金属线的铜金属线的表面上沉积钝化金属层。 或者，铜金属线层的覆盖沉积覆盖扩散层并用铜金属线填充互连孔。 执行CMP工艺以平坦化器件以去除IMD层上方的铜。 在自对准沉积工艺中，在孔的顶部封装铜金属线的铜金属线的表面上沉积钝化金属层。

公开(公告)号：US06319772B1

公开(公告)日：2001-11-20

申请号：US09697946

申请日：2000-10-30

申请人： Kheng Chok Tee ,  Randall Cher Liang Cha ,  Lap Chan

发明人： Kheng Chok Tee ,  Randall Cher Liang Cha ,  Lap Chan

IPC分类号： H01L218242

CPC分类号： H01L27/10873 ,  H01L27/10808

摘要： Low current leakage DRAM structures are achieved using a selective silicon epitaxial growth over an insulating layer on memory cell (device) areas. An insulating layer, that also serves as a stress-release layer, and a Si3N4 hard mask are patterned to leave portions over the memory cell areas. Shallow trenches are etched in the substrate and filled with a CVD oxide which is polished back to the hard mask to form shallow trench isolation (STI) around the memory cell areas. The hard mask is selectively removed to form recesses in the STI aligned over the memory cell areas exposing the underlying insulating layer. Openings are etched in the insulating layer to provide a silicon-seed surface from which is grown a selective epitaxial layer extending over the insulating layer within the recesses. After growing a gate oxide on the epitaxial layer, FETs and DRAM capacitors can be formed on the epitaxial layer. The insulating layer under the epitaxial layer drastically reduces the capacitor leakage current and improves DRAM device performance. This self-aligning method also increases memory cell density, and is integratable into current DRAM processes to reduce cost.

摘要翻译： 使用在存储器单元（器件）区域上的绝缘层上的选择性硅外延生长来实现低电流泄漏DRAM结构。 也用作应力释放层的绝缘层和Si 3 N 4硬掩模被图案化以在存储器单元区域上留下部分。 在衬底中蚀刻浅沟槽，并填充有CVD氧化物，其被抛光回硬掩模以在存储器单元区域周围形成浅沟槽隔离（STI）。 选择性地去除硬掩模，以在STI暴露下面的绝缘层的存储单元区域上对准STI中形成凹槽。 在绝缘层中蚀刻开口以提供硅种子表面，从该晶种表面生长在凹陷内的绝缘层上延伸的选择性外延层。 在外延层上生长栅极氧化物之后，可以在外延层上形成FET和DRAM电容器。 外延层下方的绝缘层大大降低了电容器的漏电流，提高了DRAM器件性能。 这种自对准方法也增加了存储单元密度，并且可以集成到当前的DRAM工艺中以降低成本。

公开(公告)号：US06730571B1

公开(公告)日：2004-05-04

申请号：US09418029

申请日：1999-10-14

申请人： Lap Chan ,  Cher Liang Cha ,  Kheng Chok Tee

发明人： Lap Chan ,  Cher Liang Cha ,  Kheng Chok Tee

IPC分类号： H01L21331

CPC分类号： H01L21/7682 ,  H01L23/5222 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

摘要： In accordance with the objectives of the invention a new method is provided for creating air gaps in a layer of IMD. First and second layers of dielectric are successively deposited over a surface; the surface contains metal lines running in an Y-direction. Trenches are etched in the first and second layer of dielectric in an X and Y-direction respectively. The trenches are filled with a layer of nitride and polished. A thin layer of oxide is deposited over the surface of the second layer of dielectric. Openings are created through the thin layer of oxide that align with the points of intersect of the nitride in the trenches in the layers of dielectric. The nitride is removed from the trenches by a wet etch, thereby opening trenches in the layers of dielectric with both sets of trenches being interconnected. The openings in the thin layer of oxide are closed, leaving a network of trenches containing air in the two layers of dielectric.

摘要翻译： 根据本发明的目的，提供了一种用于在IMD层中产生气隙的新方法。 第一和第二层电介质依次沉积在表面上; 表面包含沿Y方向延伸的金属线。 在第一和第二电介质层中分别在X和Y方向上蚀刻沟槽。 沟槽填充有一层氮化物并抛光。 在第二电介质层的表面上沉积薄层的氧化物。 通过与电介质层中的沟槽中的氮化物的交叉点对准的氧化物薄层产生开口。 通过湿蚀刻从沟槽中去除氮化物，从而在两组沟槽互连的情况下打开电介质层中的沟槽。 氧化物薄层中的开口是封闭的，留下在两层电介质中含有空气的沟槽网络。

公开(公告)号：US6100195A

公开(公告)日：2000-08-08

申请号：US222275

申请日：1998-12-28

申请人： Lap Chan ,  Kuan Pei Yap ,  Kheng Chok Tee ,  Flora S. Ip ,  Wye Boon Loh

发明人： Lap Chan ,  Kuan Pei Yap ,  Kheng Chok Tee ,  Flora S. Ip ,  Wye Boon Loh

IPC分类号： H01L21/768 ,  H01L21/44

CPC分类号： H01L21/76849 ,  H01L21/76858 ,  H01L21/76867 ,  H01L21/76886

摘要： An interconnect line on an IMD layer on a semiconductor device is formed in an interconnect hole in the IMD layer. The interconnect hole has walls and a bottom in the IMD layer. A diffusion barrier is formed on the walls and the bottom of the hole. Fill the interconnect hole with a copper metal line. Perform a CMP step to planarize the device and to remove copper above the IMD layer. Deposit a passivating metal layer on the surface of the copper metal line encapsulating the copper metal line at the top of the hole. Alternatively, a blanket deposit of a copper metal line layer covers the diffusion layer and fills the interconnect hole with a copper metal line. Perform a CMP process to planarize the device to remove copper above the IMD layer. Deposit a passivating metal layer on the surface of the copper metal line encapsulating the copper metal line at the top of the hole in a self-aligned deposition process.

公开(公告)号：US07112866B2

公开(公告)日：2006-09-26

申请号：US10796893

申请日：2004-03-09

申请人： Lap Chan ,  Cher Liang Cha ,  Kheng Chok Tee

发明人： Lap Chan ,  Cher Liang Cha ,  Kheng Chok Tee

IPC分类号： H01L29/00 ,  H01L23/48 ,  H01L21/331 ,  H01L21/4765

CPC分类号： H01L21/7682 ,  H01L23/5222 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

摘要： The invention provides a new multilevel interconnect structure of air gaps in a layer of IMD. A first layer of dielectric is provided over a surface; the surface contains metal points of contact. Trenches are provided in this first layer of dielectric. The trenches are filled with a first layer of nitride or disposable solid and polished. A second layer of dielectric is deposited over the first layer of dielectric. Trenches are formed in the second layer of dielectric, a second layer of nitride or disposable solid is deposited over the second layer of dielectric. The layer of nitride or disposable solid is polished. A thin layer of oxide is deposited over the surface of the second layer of dielectric. The thin layer of oxide is masked and etched thereby creating openings in this thin layer of oxide, these openings align with the points of intersect of the trenches in the first layer of dielectric and in the second layer of dielectric. The nitride or removable solid is removed from the trenches. The openings in the thin layer of oxide are closed off leaving a network of trenches that are filled with air in the two layers of dielectric that now function as the Inter Level Dielectric.

摘要翻译： 本发明提供了在IMD层中的空气间隙的新的多层互连结构。 在表面上提供第一层电介质; 表面含有金属接触点。 在第一层电介质中设置沟槽。 沟槽填充有第一层氮化物或一次性固体并抛光。 第二层介质沉积在第一层电介质上。 沟槽形成在第二层电介质中，第二层氮化物或一次性固体沉积在第二层电介质上。 抛光氮化物或一次性固体层。 在第二电介质层的表面上沉积薄层的氧化物。 氧化物的薄层被掩蔽和蚀刻，从而在该薄层氧化物中形成开口，这些开口与第一介电层和第二介质层中的沟槽的交叉点对准。 氮化物或可移除的固体从沟槽中去除。 氧化物薄层中的开口被封闭，留下在两层电介质中充满空气的沟槽网络，现在这两层电介质用作Inter Level Dielectric。

公开(公告)号：US06384437B1

公开(公告)日：2002-05-07

申请号：US09963411

申请日：2001-09-27

申请人： Kheng Chok Tee ,  Randall Cher Liang Cha ,  Lap Chan

发明人： Kheng Chok Tee ,  Randall Cher Liang Cha ,  Lap Chan

IPC分类号： H01L27148

CPC分类号： H01L27/10873 ,  H01L27/10808

摘要： Low current leakage DRAM structures are achieved using a selective silicon epitaxial growth over an insulating layer on memory cell (device) areas. An insulating layer, that also serves as a stress-release layer, and a Si3N4 hard mask are patterned to leave portions over the memory cell areas. Shallow trenches are etched in the substrate and filled with a CVD oxide which is polished back to the hard mask to form shallow trench isolation (STI) around the memory cell areas. The hard mask is selectively removed to form recesses in the STI aligned over the memory cell areas exposing the underlying insulating layer. Openings are etched in the insulating layer to provide a silicon-seed surface from which is grown a selective epitaxial layer extending over the insulating layer within the recesses. After growing a gate oxide on the epitaxial layer, FETs and DRAM capacitors can be formed on the epitaxial layer. The insulating layer under the epitaxial layer drastically reduces the capacitor leakage current and improves DRAM device performance. This self-aligning method also increases memory cell density, and is integratable into current DRAM processes to reduce cost.

摘要翻译： 使用在存储器单元（器件）区域上的绝缘层上的选择性硅外延生长来实现低电流泄漏DRAM结构。 也用作应力释放层的绝缘层和Si 3 N 4硬掩模被图案化以在存储器单元区域上留下部分。 在衬底中蚀刻浅沟槽，并填充有CVD氧化物，其被抛光回硬掩模以在存储器单元区域周围形成浅沟槽隔离（STI）。 选择性地去除硬掩模，以在STI暴露下面的绝缘层的存储单元区域上对准STI中形成凹槽。 在绝缘层中蚀刻开口以提供硅种子表面，从该晶种表面生长在凹陷内的绝缘层上延伸的选择性外延层。 在外延层上生长栅极氧化物之后，可以在外延层上形成FET和DRAM电容器。 外延层下方的绝缘层大大降低了电容器的漏电流，提高了DRAM器件性能。 这种自对准方法也增加了存储单元密度，并且可以集成到当前的DRAM工艺中以降低成本。

公开(公告)号：US06680239B1

公开(公告)日：2004-01-20

申请号：US09624025

申请日：2000-07-24

申请人： Cher Liang Cha ,  Kok Keng Ong ,  Alex See ,  Lap Chan

发明人： Cher Liang Cha ,  Kok Keng Ong ,  Alex See ,  Lap Chan

IPC分类号： H01L2176

CPC分类号： H01L21/76237

摘要： A method for forming shallow trench isolation (STI) with a higher aspect ratio is given. This method allows the formation of narrower and deeper trench isolation regions while avoiding substrate damage due to excessive etching and severe microloading effects. In addition, it yields uniform depth trenches while avoiding problems of etch residue at the bottom of the trench. This method is achieved by using a process where a trench is etched, and an oxide layer grown along the bottom and sidewalls of the trench. Oxygen or field isolation ions are then implanted into the bottom of the trench. A nitride spacer is then formed along the bottom and sidewalls of the trench, followed by an isotropic etch removing the nitride and oxide from the bottom of the trench. An oxide deposition then fills the trench, followed by a planarization step completing the isolation structure.

摘要翻译： 给出了一种形成具有较高纵横比的浅沟槽隔离（STI）的方法。 该方法允许形成更窄和更深的沟槽隔离区域，同时避免由于过度蚀刻和严重的微负载效应引起的基板损伤。 此外，它产生均匀的深度沟槽，同时避免沟槽底部的蚀刻残留问题。 该方法通过使用其中蚀刻沟槽的工艺和沿着沟槽的底部和侧壁生长的氧化物层来实现。 然后将氧或场隔离离子注入到沟槽的底部。 然后沿着沟槽的底部和侧壁形成氮化物间隔物，随后通过各向同性蚀刻从沟槽的底部去除氮化物和氧化物。 氧化物沉积然后填充沟槽，随后是完成隔离结构的平坦化步骤。