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    Multi-plane data order
    1.
    发明授权
    Multi-plane data order 有权

    公开(公告)号：US09773557B2

    公开(公告)日：2017-09-26

    申请号：US12552027

    申请日：2009-09-01

    申请人： Akio Goto ,  Chi-Kong Lee ,  Masayuki Urabe

    发明人： Akio Goto ,  Chi-Kong Lee ,  Masayuki Urabe

    IPC分类号： G06F12/00 ,  G06F13/00 ,  G06F13/28 ,  G11C16/10 ,  G11C7/10

    CPC分类号： G11C16/10 ,  G11C7/10 ,  G11C2207/2245 ,  G11C2216/14

    摘要： Systems, methods and computer program products for programming data into a multi-plane memory device employ a multi-plane data order. To allow multiple data pages to be programmed without a need to increase the size of page buffers, in some implementations, a data transfer scheme at which the data pages are programmed can be manipulated. Specifically, data across all channels can first be programmed into a first plane of the multi-plane flash memory device in parallel. While the data transfer program operation is in progress, data to be programmed into a succeeding plane (e.g., plane “1”) can be read into and cached in one or more page buffers. After the data transfer program for the first plane is complete, data cached in the page buffers can be immediately latched and programmed into the multi-plane flash memory device.

    Interface management control systems and methods for non-volatile semiconductor memory
    2.
    发明授权
    Interface management control systems and methods for non-volatile semiconductor memory 有权
    用于非易失性半导体存储器的接口管理控制系统和方法

    公开(公告)号：US08868852B2

    公开(公告)日：2014-10-21

    申请号：US13166340

    申请日：2011-06-22

    申请人： Chi Kong Lee ,  Siu-Hung Fred Au ,  Jungil Park ,  Hyunsuk Shin

    发明人： Chi Kong Lee ,  Siu-Hung Fred Au ,  Jungil Park ,  Hyunsuk Shin

    IPC分类号： G06F12/00 ,  G06F13/16

    CPC分类号： G06F12/0246 ,  G06F13/1668 ,  G06F2212/7201

    摘要： A control system includes a control module configured to control data transfer events of blocks of data between an interface management module and a non-volatile semiconductor memory based on at least two descriptors for each one of the data transfer events. The non-volatile semiconductor memory is prepared for a read event or a program event of the data transfer event. The interface management module and the non-volatile semiconductor memory are configured to operate within a solid-state memory drive. A command management module is configured to generate a parameter signal based on the at least two descriptors. The interface management module is configured to generate instruction signals based on the parameter signal and transmit the instruction signals to the non-volatile semiconductor memory to perform the read event or the program event.

    摘要翻译： 控制系统包括：控制模块，被配置为基于用于每个数据传输事件的至少两个描述符来控制在接口管理模块和非易失性半导体存储器之间的数据块的数据传输事件。 准备非易失性半导体存储器用于数据传输事件的读取事件或程序事件。 接口管理模块和非易失性半导体存储器被配置为在固态存储器驱动器内操作。 命令管理模块被配置为基于所述至少两个描述符生成参数信号。 接口管理模块被配置为基于参数信号生成指令信号，并将指令信号发送到非易失性半导体存储器以执行读取事件或程序事件。

    Descriptor scheduler
    3.
    发明授权
    Descriptor scheduler 有权
    描述符调度程序

    公开(公告)号：US08788781B2

    公开(公告)日：2014-07-22

    申请号：US13331749

    申请日：2011-12-20

    申请人： Chi Kong Lee ,  Siu-Hung Fred Au ,  Jungil Park ,  Hyunsuk Shin

    发明人： Chi Kong Lee ,  Siu-Hung Fred Au ,  Jungil Park ,  Hyunsuk Shin

    IPC分类号： G06F12/00

    CPC分类号： G06F3/0613 ,  G06F3/0659 ,  G06F3/068 ,  G06F3/0688

    摘要： Methods, systems and computer program products for providing a sequencer that schedules job descriptors are described. The sequencer can manage the scheduling of the job descriptors for execution based on the availability of their respective segments and channels. For example, the sequencer can check the status of the segments, and identify one or more segments that are in busy or full state, or one or more segments that are in non-busy or empty state. Based on the status check, the sequencer can execute job descriptors out of order, and in particular, give priorities to job descriptors whose associated segments are available over job descriptors whose associated segments are in busy or full state.

    摘要翻译： 描述用于提供调度作业描述符的定序器的方法，系统和计算机程序产品。 定序器可以根据其各自的段和通道的可用性来管理作业描述符的调度以便执行。 例如，定序器可以检查段的状态，并识别处于忙或满状态的一个或多个段，或处于非忙或空状态的一个或多个段。 基于状态检查，定序器可以执行无序的作业描述符，并且特别地，对相关段可用于其相关段处于忙或满状态的作业描述符的作业描述符给予优先级。

    Selectively scheduling memory accesses in parallel based on access speeds of memory
    4.
    发明授权
    Selectively scheduling memory accesses in parallel based on access speeds of memory 有权
    根据存储器的访问速度，并行地选择性地调度存储器访问

    公开(公告)号：US08762654B1

    公开(公告)日：2014-06-24

    申请号：US12484284

    申请日：2009-06-15

    申请人： Xueshi Yang ,  Chi Kong Lee

    发明人： Xueshi Yang ,  Chi Kong Lee

    IPC分类号： G06F12/00 ,  G06F13/00 ,  G06F13/28 ,  G11C8/00 ,  G11C16/04 ,  G11C11/34

    CPC分类号： G06F3/0611 ,  G06F3/061 ,  G06F3/0613 ,  G06F3/0655 ,  G06F3/0659 ,  G06F3/0679 ,  G06F12/0246 ,  G11C7/22 ,  G11C11/5628 ,  G11C11/5642 ,  G11C2207/2209

    摘要： Devices, systems, methods, and other embodiments associated with selectively scheduling memory accesses in parallel are described. In one embodiment, a method determines an access speed for a page request. The access speed is a number of clock cycles used to access a memory device of a group of memory devices. The page request is a request to access a memory page mapped to the memory device. Different page requests are selectively scheduled to access different memory devices in parallel. The different page requests access the different memory devices in a same number of clock cycles.

    摘要翻译： 描述了与并行选择性地调度存储器访问相关联的设备，系统，方法和其他实施例。 在一个实施例中，一种方法确定寻呼请求的访问速度。 访问速度是用于访问一组存储器设备的存储器件的多个时钟周期。 页面请求是访问映射到存储器设备的存储器页面的请求。 选择性地调度不同的页面请求以并行访问不同的存储器件。 不同的页面请求以相同数量的时钟周期访问不同的存储器设备。

    Flexible sequence design architecture for solid state memory controller
    6.
    发明授权
    Flexible sequence design architecture for solid state memory controller 有权
    固态存储器控制器的灵活序列设计架构

    公开(公告)号：US08255615B1

    公开(公告)日：2012-08-28

    申请号：US12569089

    申请日：2009-09-29

    申请人： Tony Yoon ,  Hyunsuk Shin ,  Chi-Kong Lee

    发明人： Tony Yoon ,  Hyunsuk Shin ,  Chi-Kong Lee

    IPC分类号： G06F13/14

    CPC分类号： G06F3/0659 ,  G06F3/061 ,  G06F3/0688 ,  G06F11/1068 ,  G06F12/0246 ,  G06F13/1668 ,  G06F13/1689

    摘要： Methods, systems and computer program products for sending one or more commands to one or more flash memory devices using a solid state controller and receiving information associated with the commands from the flash memory devices are described. In some implementations, the solid state controller includes a sequencer to forward the commands to the flash memory devices on behalf of the firmware.

    摘要翻译： 描述用于使用固态控制器向一个或多个闪存设备发送一个或多个命令并接收与来自闪存设备的命令相关联的信息的方法，系统和计算机程序产品。 在一些实施方式中，固态控制器包括用于代表固件将命令转发到闪存设备的定序器。

    Flexible sequencer design architecture for solid state memory controller
    8.
    发明授权
    Flexible sequencer design architecture for solid state memory controller 有权
    灵活的音序器设计架构，用于固态存储器控制器

    公开(公告)号：US08185713B2

    公开(公告)日：2012-05-22

    申请号：US12212636

    申请日：2008-09-17

    申请人： Hyunsuk Shin ,  Chi Kong Lee ,  Tony Yoon

    发明人： Hyunsuk Shin ,  Chi Kong Lee ,  Tony Yoon

    IPC分类号： G06F13/18

    CPC分类号： G06F13/1668 ,  G06F3/061 ,  G06F3/0659 ,  G06F3/0688

    摘要： A method and apparatus for controlling access to solid state memory devices which may allow maximum parallelism on accessing solid state memory devices with minimal interventions from firmware. To reduce the waste of host time, multiple flash memory devices may be connected to each channel. A job/descriptor architecture may be used to increase parallelism by allowing each memory device to operate separately. A job may be used to represent a read, write or erase operation. When firmware wants to assign a job to a device, it may issue a descriptor, which may contain information about the target channel, the target device, the type of operation, etc. The firmware may provide descriptors without waiting for a response from a memory device, and several jobs may be issued continuously to form a job queue. After the firmware finishes programming descriptors, a sequencer may handle the remaining work so that the firmware may concentrate on other tasks.

    摘要翻译： 用于控制对固态存储器件的访问的方法和装置，其可以允许以最少的固件干预来访问固态存储器设备的最大并行性。 为了减少主机时间的浪费，可以将多个闪存设备连接到每个通道。 通过允许每个存储器件分开操作，可以使用作业/描述符架构来增加并行性。 可以使用作业来表示读取，写入或擦除操作。 当固件想要将作业分配给设备时，它可以发布描述符，其可以包含关于目标通道，目标设备，操作类型等的信息。固件可以提供描述符而不等待来自存储器的响应 设备，并且可以连续地发出几个作业以形成作业队列。 固件完成编程描述符后，定序器可以处理剩余的工作，以便固件可以专注于其他任务。

    Nonvolatile Memory System
    9.
    发明申请
    Nonvolatile Memory System 有权
    非易失性存储系统

    公开(公告)号：US20120023284A1

    公开(公告)日：2012-01-26

    申请号：US13230624

    申请日：2011-09-12

    申请人： Zining Wu ,  Lau Nguyen ,  Pantas Sutardja ,  Chi-Kong Lee ,  Tony Yoon

    发明人： Zining Wu ,  Lau Nguyen ,  Pantas Sutardja ,  Chi-Kong Lee ,  Tony Yoon

    IPC分类号： G06F12/00

    CPC分类号： G06F3/0688 ,  G06F3/0619 ,  G06F3/0661 ,  G06F11/1068 ,  G06F12/0246

    摘要： A memory system including a nonvolatile memory, and a memory control module. The nonvolatile memory includes a plurality of memory cells arranged among a plurality of physical memory blocks, wherein each physical memory block is of a predetermined size. The memory control module includes a write path module and a read path module. In response to the memory control module receiving data in a first format such that the data is evenly distributable among the plurality of physical memory blocks, the write path module modifies the first format of the data into a second format prior to writing the data to the plurality of physical memory blocks. The second format of the data is such that the data is no longer evenly distributable among the plurality of physical memory blocks. The read path module is configured to read the data from the nonvolatile memory in accordance with the second format.

    摘要翻译： 一种包括非易失性存储器和存储器控制模块的存储器系统。 非易失性存储器包括布置在多个物理存储器块之间的多个存储器单元，其中每个物理存储块具有预定尺寸。 存储器控制模块包括写入路径模块和读取路径模块。 响应于存储器控制模块以第一格式接收数据使得数据在多个物理存储器块之间可均匀地分配，写入路径模块在将数据写入到第二格式之前将数据的第一格式修改为第二格式 多个物理存储器块。 数据的第二格式使得数据不再能够在多个物理存储器块之间均匀分配。 读路径模块被配置为根据第二格式从非易失性存储器读取数据。

    NONVOLATILE MEMORY SYSTEM
    10.
    发明申请
    NONVOLATILE MEMORY SYSTEM 有权
    非易失性存储系统

    公开(公告)号：US20080195810A1

    公开(公告)日：2008-08-14

    申请号：US12025371

    申请日：2008-02-04

    申请人： Zining Wu ,  Lau Nguyen ,  Pantas Sutardja ,  Chi-Kong Lee ,  Tony Yoon

    发明人： Zining Wu ,  Lau Nguyen ,  Pantas Sutardja ,  Chi-Kong Lee ,  Tony Yoon

    IPC分类号： G06F12/00

    CPC分类号： G06F3/0688 ,  G06F3/0619 ,  G06F3/0661 ,  G06F11/1068 ,  G06F12/0246

    摘要： A nonvolatile (NV) memory system includes a memory control module that encodes data to provide encoded logical data structures. The system also includes NV memory that includes X arrays that include physical data structures that differ in size from the encoded logical data structures. The memory control module writes/reads from the NV memory according to the encoded logical data structures. X is an integer greater than or equal to 1.

    摘要翻译： 非易失性（NV）存储器系统包括对数据进行编码以提供编码的逻辑数据结构的存储器控​​制模块。 该系统还包括NV存储器，其包括X阵列，其包括与编码的逻辑数据结构不同的物理数据结构。 存储器控制模块根据编码的逻辑数据结构从NV存储器读/写。 X是大于或等于1的整数。