公开(公告)号：US20130049107A1

公开(公告)日：2013-02-28

申请号：US13576702

申请日：2010-06-29

申请人： Koon Chong So

发明人： Koon Chong So

IPC分类号： H01L21/336 ,  H01L29/78

CPC分类号： H01L29/7813 ,  H01L29/0661 ,  H01L29/407 ,  H01L29/456 ,  H01L29/66727 ,  H01L29/66734 ,  H01L29/7811

摘要： A trench semiconductor power device and a fabrication method. The fabrication method includes: eroding an n epitaxial layer on an n+ substrate to form multiple gate trenches, and implanting with dopants to form source regions and P type base regions, respectively; eroding an interlayer dielectric to form a trench plug; and eroding an aluminum copper alloy to form a metal pad layer and wires. The method forms the source regions and the base regions by directly implanting, does not need source region masks and base region masks, has a simple fabrication process, and improves the quality and reliability of the device.

摘要翻译： 沟槽半导体功率器件及其制造方法。 该制造方法包括：蚀刻n +衬底上的n外延层以形成多个栅极沟槽，并用掺杂剂注入以分别形成源极区域和P型基极区域; 腐蚀层间电介质以形成沟槽塞; 并腐蚀铝铜合金以形成金属焊盘层和电线。 该方法通过直接注入形成源区和基区，不需要源区掩模和基区掩模，具有简单的制造工艺，提高了器件的质量和可靠性。

公开(公告)号：US20110193176A1

公开(公告)日：2011-08-11

申请号：US13091410

申请日：2011-04-21

申请人： Samuel Anderson ,  Koon Chong So

发明人： Samuel Anderson ,  Koon Chong So

IPC分类号： H01L27/06 ,  H01L29/06

CPC分类号： H01L29/7813 ,  H01L21/26586 ,  H01L29/0634 ,  H01L29/0653 ,  H01L29/66143 ,  H01L29/66734 ,  H01L29/7811 ,  H01L29/872

摘要： A semiconductor device includes unlined and sealed trenches and methods for forming the unlined and sealed trenches. More particularly, a superjunction semiconductor device includes unlined, and sealed trenches. The trench has sidewalls formed of the semiconductor material. The trench is sealed with a sealing material such that the trench is air-tight. First and second regions are separated by the trench. The first region may include a superjunction Schottky diode or MOSFET. In an alternative embodiment, a plurality of regions are separated by a plurality of unlined and sealed trenches.

摘要翻译： 半导体器件包括无衬里和密封的沟槽以及用于形成无衬里和密封沟槽的方法。 更具体地说，超结半导体器件包括无衬里和密封的沟槽。 沟槽具有由半导体材料形成的侧壁。 沟槽用密封材料密封，使得沟槽是气密的。 第一和第二区域被沟槽分开。 第一区域可以包括超连接肖特基二极管或MOSFET。 在替代实施例中，多个区域被多个无衬里和密封的沟槽隔开。

公开(公告)号：US07049194B2

公开(公告)日：2006-05-23

申请号：US10725326

申请日：2003-12-01

申请人： Fwu-Iuan Hshieh ,  Koon Chong So ,  William John Nelson ,  John E. Amato

发明人： Fwu-Iuan Hshieh ,  Koon Chong So ,  William John Nelson ,  John E. Amato

IPC分类号： H01L21/336

CPC分类号： H01L29/7813 ,  H01L29/0653 ,  H01L29/41741 ,  H01L29/41766 ,  H01L29/7809 ,  H01L29/7811

摘要： A trench DMOS transistor device that comprises: (a) a substrate of a first conductivity type; (b) an epitaxial layer of first conductivity type over the substrate, wherein the epitaxial layer has a lower majority carrier concentration than the substrate; (c) a trench extending into the epitaxial layer from an upper surface of the epitaxial layer; (d) an insulating layer lining at least a portion of the trench; (e) a conductive region within the trench adjacent the insulating layer; (f) a body region of a second conductivity type provided within an upper portion of the epitaxial layer and adjacent the trench; (g) a source region of first conductivity type within an upper portion of the body region and adjacent the trench; and (h) one or more low resistivity deep regions extending into the device from an upper surface of the epitaxial layer. The low resistivity deep region acts to provide electrical contact with the substrate, which is a common drain region for the device. By constructing a trench DMOS transistor device in this fashion, source, drain and gate contacts can all be provided on a single surface of the device.

公开(公告)号：US06849899B2

公开(公告)日：2005-02-01

申请号：US10673887

申请日：2003-09-29

申请人： Fwu-Iuan Hshieh ,  Koon Chong So

发明人： Fwu-Iuan Hshieh ,  Koon Chong So

IPC分类号： H01L21/336 ,  H01L29/423 ,  H01L29/45 ,  H01L29/49 ,  H01L29/78 ,  H01L29/76

CPC分类号： H01L29/7813 ,  H01L29/4232 ,  H01L29/4236 ,  H01L29/42372 ,  H01L29/4238 ,  H01L29/456 ,  H01L29/4916 ,  H01L29/4925 ,  H01L29/4933

摘要： A method for making trench DMOS is provided that utilizes polycide and refractory techniques to make trench DMOS which exhibit low gate resistance, low gate capacitance, reduced distributed RC gate propagation delay, and improved switching speeds for high frequency applications.

摘要翻译： 提供了制造沟槽DMOS的方法，其利用多硅化物和难熔技术来制造出具有低栅极电阻，低栅极电容，降低的分布式RC栅极传播延迟以及用于高频应用的改进的开关速度的沟槽DMOS。

公开(公告)号：US06621107B2

公开(公告)日：2003-09-16

申请号：US09938253

申请日：2001-08-23

申请人： Richard A. Blanchard ,  Fwu-Iuan Hshieh ,  Koon Chong So

发明人： Richard A. Blanchard ,  Fwu-Iuan Hshieh ,  Koon Chong So

IPC分类号： H01L2974

CPC分类号： H01L29/7813 ,  H01L29/0619 ,  H01L29/0623 ,  H01L29/0696 ,  H01L29/1095 ,  H01L29/41766 ,  H01L29/7806 ,  H01L29/872

摘要： A merged device is that comprises a plurality of MOSFET cells and a plurality of Schottky rectifier cells, as well as a method of designing and making the same. According to an embodiment of the invention, the MOSFET cells comprise: (a) a source region of first conductivity type formed within an upper portion of a semiconductor region, (b) a body region of second conductivity type formed within a middle portion of the semiconductor region, (c) a drain region of first conductivity type formed within a lower portion of the semiconductor region, and (d) a gate region provided adjacent the source region, the body region, and the drain region. The Schottky diode cells in this embodiment are disposed within a trench network and comprise a conductor portion in Schottky rectifying contact with the lower portion of the semiconductor region. At least one MOSFET cell gate region is positioned along a sidewall of the trench network and adjacent at least one Schottky diode cell in this embodiment.

摘要翻译： 合并器件包括多个MOSFET单元和多个肖特基整流器单元，以及其设计和制造方法。 根据本发明的实施例，MOSFET单元包括：（a）形成在半导体区域的上部内的第一导电类型的源极区域，（b）形成在半导体区域的中间部分内的第二导电类型的体区域 半导体区域，（c）形成在半导体区域的下部内的第一导电类型的漏极区域，以及（d）设置在源极区域，体区域和漏极区域附近的栅极区域。 该实施例中的肖特基二极管电池设置在沟槽网络内，并且包括与半导体区域的下部肖特基整流接触的导体部分。 在该实施例中，至少一个MOSFET单元栅极区沿着沟槽网络的侧壁定位并且邻近至少一个肖特基二极管单元。

公开(公告)号：US06558984B2

公开(公告)日：2003-05-06

申请号：US10078994

申请日：2002-02-19

申请人： Fwu-Iuan Hshieh ,  Koon Chong So ,  John E. Amato

发明人： Fwu-Iuan Hshieh ,  Koon Chong So ,  John E. Amato

IPC分类号： H01L21332

CPC分类号： H01L29/66143 ,  H01L29/417 ,  H01L29/872

摘要： A trench Schottky barrier and a method of making the same in which the rectifier has a semiconductor region having first and second opposing faces; the semiconductor region having a drift region of a first conductivity type adjacent the first face and a cathode region of the first conductivity type adjacent the second face; the drift region having a lower net doping concentration than that of the cathode region. The rectifier also has a plurality of trenches extending into the semiconductor region from the first face; the trenches defining a plurality of mesas within the semiconductor region, and the trenches forming a plurality of trench intersections. The rectifier further includes an oxide layer covering the semiconductor region on the bottoms of the trenches and on lower portions of sidewalls of the trenches, a polysilicon region disposed over the oxide layer within the trenches, and insulating regions at the trench intersections that cover a portion of the polysilicon region and a portion of the oxide layer.

摘要翻译： 沟槽肖特基势垒及其制造方法，其中整流器具有具有第一和第二相对面的半导体区域; 所述半导体区域具有与所述第一面相邻的第一导电类型的漂移区域和与所述第二面部相邻的所述第一导电类型的阴极区域; 漂移区具有比阴极区更低的净掺杂浓度。 整流器还具有从第一面延伸到半导体区域中的多个沟槽; 所述沟槽限定所述半导体区域内的多个台面，并且所述沟槽形成多个沟槽交叉点。 整流器还包括覆盖沟槽底部的半导体区域和沟槽侧壁的下部的氧化物层，设置在沟槽内的氧化物层上的多晶硅区域以及覆盖部分的沟槽交点处的绝缘区域 的多晶硅区域和氧化物层的一部分。

公开(公告)号：US06475884B2

公开(公告)日：2002-11-05

申请号：US09924855

申请日：2001-08-08

申请人： Fwu-Iuan Hshieh ,  Koon Chong So ,  Yan Man Tsui

发明人： Fwu-Iuan Hshieh ,  Koon Chong So ,  Yan Man Tsui

IPC分类号： H01L2136

CPC分类号： H01L29/7813 ,  H01L21/3083 ,  H01L29/7811

摘要： In a first aspect of the invention, a modified semiconductor substrate is provided. The modified substrate comprises: (1) a semiconductor substrate; (2) at least one buffer layer provided over at least a portion of the substrate; and (3) a plurality of trenches comprising (a) a plurality of internal trenches that extend into the semiconductor substrate and (b) at least one shallow peripheral trench that extends into the at least one buffer layer but does not extend into the semiconductor substrate. In another aspect, a method of selectively providing trenches in a semiconductor substrate is provided. According to a further aspect of the invention, a trench DMOS transistor structure that includes at least one peripheral trench and a plurality of internal trenches is provided. The structure comprises: (1) a substrate of a first conductivity type; (2) a body region on the substrate having a second conductivity type, wherein the peripheral and internal trenches extend through the body region; (3) an insulating layer that lines each of the peripheral and internal trenches; (4) a first conductive electrode overlying each insulating layer; and (5) source regions of the first conductivity type in the body region adjacent to the each internal trench, but not adjacent to the at least one peripheral trench.

摘要翻译： 在本发明的第一方面中，提供了一种改进的半导体衬底。 改性基板包括：（1）半导体衬底; （2）在衬底的至少一部分上提供的至少一个缓冲层; 和（3）多个沟槽，包括（a）延伸到半导体衬底中的多个内部沟槽和（b）延伸到至少一个缓冲层中但不延伸到半导体衬底中的至少一个浅外围沟槽 。 另一方面，提供了一种在半导体衬底中选择性地提供沟槽的方法。 根据本发明的另一方面，提供了包括至少一个外围沟槽和多个内部沟槽的沟槽DMOS晶体管结构。 该结构包括：（1）第一导电类型的衬底; （2）具有第二导电类型的衬底上的主体区域，其中所述外围和内部沟槽延伸穿过所述身体区域; （3）对每个外围和内部沟槽进行排列的绝缘层; （4）覆盖每个绝缘层的第一导电电极; 和（5）与所述每个内部沟槽相邻但不与所述至少一个周边沟槽相邻的所述主体区域中的所述第一导电类型的源极区域。

公开(公告)号：US06420768B1

公开(公告)日：2002-07-16

申请号：US09737357

申请日：2000-12-15

申请人： Fwu-Iuan Hshieh ,  Koon Chong So ,  John E. Amato

发明人： Fwu-Iuan Hshieh ,  Koon Chong So ,  John E. Amato

IPC分类号： H01L27095

CPC分类号： H01L29/66143 ,  H01L29/417 ,  H01L29/872

摘要： A trench Schottky barrier rectifier and a method of making the same in which the rectifier has a semiconductor region having first and second opposing faces; the semiconductor region having a drift region of first conductivity type adjacent the first face and a cathode region of the first conductivity type adjacent the second face; the drift region having a lower net doping concentration than that of the cathode region. The rectifier also has a plurality of trenches extending into the semiconductor region from the first face; the trenches defining a plurality of mesas within the semiconductor region, and the trenches forming a plurality of trench intersections. The rectifier further includes an oxide layer covering the semiconductor region on bottoms of the trenches and on lower portions of sidewalls of the trenches, a polysilicon region disposed over the oxide layer within the trenches, and insulating regions at the trench intersections that cover a portion of the polysilicon region and a portion of the oxide layer.

摘要翻译： 沟槽肖特基势垒整流器及其制造方法，其中整流器具有具有第一和第二相对面的半导体区域; 所述半导体区域具有与所述第一面相邻的第一导电类型的漂移区域和与所述第二面部相邻的所述第一导电类型的阴极区域; 漂移区具有比阴极区更低的净掺杂浓度。 整流器还具有从第一面延伸到半导体区域中的多个沟槽; 所述沟槽限定所述半导体区域内的多个台面，并且所述沟槽形成多个沟槽交叉点。 整流器还包括覆盖沟槽底部的半导体区域和沟槽的侧壁的下部的氧化物层，设置在沟槽内的氧化物层上的多晶硅区域以及覆盖部分的沟槽交点处的绝缘区域 多晶硅区域和氧化物层的一部分。

公开(公告)号：US06376315B1

公开(公告)日：2002-04-23

申请号：US09540856

申请日：2000-03-31

申请人： Fwu-Iuan Hshieh ,  Koon Chong So

发明人： Fwu-Iuan Hshieh ,  Koon Chong So

IPC分类号： H01L21336

CPC分类号： H01L29/1095

摘要： A method of manufacturing one or more trench DMOS transistors is provided. In this method, one or more or more body regions adjacent one or more trenches are provided. The one or more trenches are lined with a first insulating layer. A portion of the first insulating layer is removed along at least the upper sidewalls of the trenches, exposing portions of the body regions. An oxide layer is then formed over at least the exposed portions of the body regions, resulting in regions of reduced majority carrier concentration within the body regions adjacent the oxide layer. This modification of the majority carrier concentration in the body regions is advantageous in that a low threshold voltage can be established within the DMOS transistor without resorting to a thinner gate oxide (which would reduce yield and switching speed) and without substantially increasing the likelihood of punch-through.

摘要翻译： 提供制造一个或多个沟槽DMOS晶体管的方法。 在该方法中，提供与一个或多个沟槽相邻的一个或多个或多个主体区域。 一个或多个沟槽衬有第一绝缘层。 第一绝缘层的一部分至少沿着沟槽的上侧壁去除，暴露身体区域的部分。 然后在身体区域的至少暴露部分上形成氧化物层，导致与氧化物层相邻的体区内的载流子浓度降低的区域。 体内区域中多数载流子浓度的这种修改是有利的，因为可以在DMOS晶体管内建立低阈值电压，而不需要使用更薄的栅极氧化物（这将降低产率和开关速度），而且基本上不增加冲击的可能性 -通过。

公开(公告)号：US6048759A

公开(公告)日：2000-04-11

申请号：US21879

申请日：1998-02-11

申请人： Fwu-Iuan Hshieh ,  Koon Chong So ,  Yan Man Tsui ,  Danny Chi Nim

发明人： Fwu-Iuan Hshieh ,  Koon Chong So ,  Yan Man Tsui ,  Danny Chi Nim

IPC分类号： H01L21/336 ,  H01L29/10 ,  H01L29/423 ,  H01L29/78 ,  H01L21/8238

CPC分类号： H01L29/66712 ,  H01L29/1095 ,  H01L29/42368 ,  H01L29/7802 ,  H01L29/0638

摘要： This invention discloses a DMOS power device supported on a substrate of a first conductivity type functioning as a drain. The DMOS power device includes a polysilicon-over-double-gate-oxide gate disposed on the substrate includes a polysilicon layer disposed over a double-gate-oxide structure having a central thick-gate-oxide segment surrounded by a thin-gate-oxide layer with a thickness of about one-fourth to one-half of a thickness of the thick-gate-oxide segment. The DMOS power device further includes a body region of a second conductivity type disposed in the substrate underneath the thin-gate-oxide layer around edges of the central thick-gate-oxide segment the body region extending out laterally to a neighboring device circuit element. The DMOS power device further includes a source region of the first conductivity type disposed in the substrate encompassed in the body region having a portion extending laterally underneath the thin-gate-oxide layer. The DMOS power device further includes an insulation layer covering the polysilicon-over-double-gate-oxide gate with contact openings above the substrate exposing the source region and the body region.

摘要翻译： 本发明公开了一种DMOS功率器件，其被支撑在用作漏极的第一导电类型的衬底上。 DMOS功率器件包括设置在衬底上的多晶硅 - 双栅极氧化物栅极，其包括设置在双栅极 - 氧化物结构上的多晶硅层，其具有由薄栅氧化物围绕的中心厚栅氧化层段 厚度为厚栅极 - 氧化物段的厚度的大约四分之一到一半的层。 DMOS功率器件还包括第二导电类型的主体区域，其设置在薄栅氧化层下方的衬底中，围绕中心厚栅氧化物段的边缘，主体区域横向延伸到相邻的器件电路元件。 DMOS功率器件还包括设置在基体中的第一导电类型的源极区域，该基极包含在具有在薄栅氧化层下方横向延伸的部分的主体区域中。 DMOS功率器件还包括覆盖多晶硅超双栅极氧化物栅极的绝缘层，其具有暴露源极区域和体区域的衬底上方的接触开口。