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    Method of forming dual damascene semiconductor device
    2.
    发明授权
    Method of forming dual damascene semiconductor device 有权
    双镶嵌半导体器件的形成方法

    公开(公告)号：US08034722B2

    公开(公告)日：2011-10-11

    申请号：US11279055

    申请日：2006-04-07

    申请人： Chih-Han Lin ,  Kun-Ei Chen

    发明人： Chih-Han Lin ,  Kun-Ei Chen

    IPC分类号： H01L21/302 ,  H01L21/461

    CPC分类号： H01L21/76829 ,  H01L21/76804 ,  H01L21/76807 ,  H01L21/76808

    摘要： A method of forming a dual damascene includes forming first, second and third material layers sequentially over a substrate. The first, second and third material layers have first, second and third thicknesses, respectively. An opening is etched within the first material layer while a portion or all of the thickness of the third layer is simultaneously removed. The ratio of the depth of the opening and the thickness of the third material layer removed, correspond to an etch selectivity of the first material layer and the second material layer. The etching operation may be automatically terminated to produce the opening with a predetermined depth.

    摘要翻译： 形成双镶嵌层的方法包括在衬底上依次形成第一，第二和第三材料层。 第一，第二和第三材料层分别具有第一，第二和第三厚度。 在第一材料层内蚀刻开口，同时去除第三层的厚度的一部分或全部。 开口的深度与去除的第三材料层的厚度的比率对应于第一材料层和第二材料层的蚀刻选择性。 蚀刻操作可以自动终止以产生具有预定深度的开口。

    Non-invasive wafer transfer position diagnosis and calibration
    3.
    发明授权
    Non-invasive wafer transfer position diagnosis and calibration 失效
    非侵入性晶片转移位置诊断和校准

    公开(公告)号：US06965432B2

    公开(公告)日：2005-11-15

    申请号：US10165006

    申请日：2002-06-07

    申请人： Yu-Yi Wu ,  Kun-Ei Chen ,  San-Ching Lin

    发明人： Yu-Yi Wu ,  Kun-Ei Chen ,  San-Ching Lin

    IPC分类号： G03F7/20 ,  H01L21/00 ,  H01L21/68 ,  G01B11/00

    CPC分类号： H01L21/67259 ,  G03F7/7075 ,  H01L21/681

    摘要： An apparatus and method for detecting mispositioned wafers attributable to transfer shift of the wafer are disclosed. A calibration wafer has a target region comprising a pattern of optically distinguishable features from which is determined the position of the calibration wafer within the chamber subsequent to its transfer therein. Preferably, the features comprise a pattern of colors that can be detected by spectroscopy. A preferred form and manner of providing such color features is by way of dielectric thin film filters.

    摘要翻译： 公开了一种用于检测归因于晶片的转移移位的错位晶片的装置和方法。 校准晶片具有包括可区分光学特征的图案的目标区域，其中确定校准晶片在其内转移之后的腔室内的位置。 优选地，特征包括可以通过光谱法检测的颜色图案。 提供这种颜色特征的优选形式和方式是通过介电薄膜滤光器。

    System and method of monitoring and controlling atomic layer deposition of tungsten
    4.
    发明授权
    System and method of monitoring and controlling atomic layer deposition of tungsten 有权
    监测和控制钨原子层沉积的系统和方法

    公开(公告)号：US08900886B2

    公开(公告)日：2014-12-02

    申请号：US13486270

    申请日：2012-06-01

    申请人： Kun-Ei Chen ,  Jen-Yi Chen ,  Yi-Chung Lin ,  Chen-Chieh Chiang ,  Ling-Sung Wang

    发明人： Kun-Ei Chen ,  Jen-Yi Chen ,  Yi-Chung Lin ,  Chen-Chieh Chiang ,  Ling-Sung Wang

    IPC分类号： H01L21/66

    CPC分类号： C23C16/52 ,  C23C16/14 ,  C23C16/45527 ,  H01J37/32981

    摘要： A method of semiconductor processing comprises providing a semiconductor wafer in a processing chamber; feeding at least one tungsten-containing precursor in a gas state into the processing chamber for atomic layer deposition (ALD) of tungsten; feeding at least one reducing chemical in a gas state into the processing chamber; and monitoring a concentration of at least one gaseous byproduct in the chamber; and providing a signal indicating concentration of the at least one gaseous byproduct in the chamber. The byproduct is produced by a reaction between the at least one tungsten-containing precursor and the at least one reducing chemical during the ALD.

    摘要翻译： 一种半导体处理方法包括在处理室中设置半导体晶片; 将至少一种以气体状态的含钨前体进料到用于钨的原子层沉积（ALD）的处理室中; 将至少一种气体状态的还原化学品进料到所述处理室中; 以及监测所述室中的至少一种气态副产物的浓度; 以及提供指示所述室中所述至少一种气态副产物的浓度的信号。 在ALD期间，副产物通过至少一种含钨前体与至少一种还原化学物质之间的反应产生。

    Method for forming semiconductor device
    6.
    发明授权
    Method for forming semiconductor device 有权
    半导体器件形成方法

    公开(公告)号：US08586486B2

    公开(公告)日：2013-11-19

    申请号：US13327947

    申请日：2011-12-16

    申请人： Jen-Yi Chen ,  Kun-Ei Chen ,  Ling-Sung Wang ,  Chen-Chieh Chiang

    发明人： Jen-Yi Chen ,  Kun-Ei Chen ,  Ling-Sung Wang ,  Chen-Chieh Chiang

    IPC分类号： H01L21/31

    CPC分类号： H01L21/76802 ,  H01L21/0271 ,  H01L21/3105 ,  H01L21/31144 ,  H01L21/76826

    摘要： A method of patterning a material layer of a semiconductor device is disclosed, the method including treating a material layer above a semiconductor substrate with plasma oxygen; depositing a layer of photoresist over a first surface of the material layer after the treating of the material layer; patterning the layer of photoresist, thereby forming a patterned photoresist, exposing portions of the material layer; etching the exposed portions of at least the material layer to form at least one contact via in the material layer extending to a source or drain region of a device at a surface of the substrate; and removing the patterned photoresist from the first surface of the material layer.

    摘要翻译： 公开了一种图案化半导体器件的材料层的方法，该方法包括用等离子体氧处理半导体衬底之上的材料层; 在处理材料层之后，在材料层的第一表面上沉积光致抗蚀剂层; 图案化光致抗蚀剂层，从而形成图案化的光致抗蚀剂，暴露材料层的部分; 蚀刻至少材料层的暴露部分以在材料层中形成至少一个接触通孔，延伸到衬底的表面处的器件的源极或漏极区域; 以及从所述材料层的第一表面去除所述图案化的光致抗蚀剂。

    METHOD FOR FORMING SEMICONDUCTOR DEVICE
    7.
    发明申请
    METHOD FOR FORMING SEMICONDUCTOR DEVICE 有权
    形成半导体器件的方法

    公开(公告)号：US20130157467A1

    公开(公告)日：2013-06-20

    申请号：US13327947

    申请日：2011-12-16

    申请人： Jen-Yi CHEN ,  Kun-Ei CHEN ,  Ling-Sung WANG ,  Chen-Chieh CHANG

    发明人： Jen-Yi CHEN ,  Kun-Ei CHEN ,  Ling-Sung WANG ,  Chen-Chieh CHANG

    IPC分类号： H01L21/311

    CPC分类号： H01L21/76802 ,  H01L21/0271 ,  H01L21/3105 ,  H01L21/31144 ,  H01L21/76826

    摘要： A method of patterning a material layer of a semiconductor device is disclosed, the method including treating a material layer above a semiconductor substrate with plasma oxygen; depositing a layer of photoresist over a first surface of the material layer after the treating of the material layer; patterning the layer of photoresist, thereby forming a patterned photoresist, exposing portions of the material layer; etching the exposed portions of at least the material layer to form at least one contact via in the material layer extending to a source or drain region of a device at a surface of the substrate; and removing the patterned photoresist from the first surface of the material layer.

    摘要翻译： 公开了一种图案化半导体器件的材料层的方法，该方法包括用等离子体氧处理半导体衬底之上的材料层; 在处理材料层之后，在材料层的第一表面上沉积光致抗蚀剂层; 图案化光致抗蚀剂层，从而形成图案化的光致抗蚀剂，暴露材料层的部分; 蚀刻至少材料层的暴露部分以在材料层中形成至少一个接触通孔，延伸到衬底的表面处的器件的源极或漏极区域; 以及从所述材料层的第一表面去除所述图案化的光致抗蚀剂。

    SYSTEM AND METHOD OF MONITORING AND CONTROLLING ATOMIC LAYER DEPOSITION OF TUNGSTEN
    8.
    发明申请
    SYSTEM AND METHOD OF MONITORING AND CONTROLLING ATOMIC LAYER DEPOSITION OF TUNGSTEN 有权
    监测和控制原子层沉积的系统和方法

    公开(公告)号：US20130323859A1

    公开(公告)日：2013-12-05

    申请号：US13486270

    申请日：2012-06-01

    申请人： Kun-Ei CHEN ,  Jen-Yi CHEN ,  Yi-Chung LIN ,  Chen-Chieh CHIANG ,  Ling-Sung WANG

    发明人： Kun-Ei CHEN ,  Jen-Yi CHEN ,  Yi-Chung LIN ,  Chen-Chieh CHIANG ,  Ling-Sung WANG

    IPC分类号： H01L21/66 ,  C23C16/52

    CPC分类号： C23C16/52 ,  C23C16/14 ,  C23C16/45527 ,  H01J37/32981

    摘要： A method of semiconductor processing comprises providing a semiconductor wafer in a processing chamber; feeding at least one tungsten-containing precursor in a gas state into the processing chamber for atomic layer deposition (ALD) of tungsten; feeding at least one reducing chemical in a gas state into the processing chamber; and monitoring a concentration of at least one gaseous byproduct in the chamber; and providing a signal indicating concentration of the at least one gaseous byproduct in the chamber. The byproduct is produced by a reaction between the at least one tungsten-containing precursor and the at least one reducing chemical during the ALD.

    摘要翻译： 一种半导体处理方法包括在处理室中设置半导体晶片; 将至少一种以气体状态的含钨前体进料到用于钨的原子层沉积（ALD）的处理室中; 将至少一种气体状态的还原化学品进料到所述处理室中; 以及监测所述室中的至少一种气态副产物的浓度; 以及提供指示所述室中所述至少一种气态副产物的浓度的信号。 在ALD期间，副产物通过至少一种含钨前体与至少一种还原化学物质之间的反应产生。

    METHOD OF FORMING DUAL DAMASCENE SEMICONDUCTOR DEVICE
    9.
    发明申请
    METHOD OF FORMING DUAL DAMASCENE SEMICONDUCTOR DEVICE 有权
    形成双重半导体半导体器件的方法

    公开(公告)号：US20070238306A1

    公开(公告)日：2007-10-11

    申请号：US11279055

    申请日：2006-04-07

    申请人： Chih-Han Lin ,  Kun-Ei Chen

    发明人： Chih-Han Lin ,  Kun-Ei Chen

    IPC分类号： H01L21/467

    CPC分类号： H01L21/76829 ,  H01L21/76804 ,  H01L21/76807 ,  H01L21/76808

    摘要： A method of forming a dual damascene includes forming first, second and third material layers sequentially over a substrate. The first, second and third material layers have first, second and third thicknesses, respectively. An opening is etched within the first material layer while a portion or all of the thickness of the third layer is simultaneously removed. The ratio of the depth of the opening and the thickness of the third material layer removed, correspond to an etch selectivity of the first material layer and the second material layer. The etching operation may be automatically terminated to produce the opening with a predetermined depth.

    摘要翻译： 形成双镶嵌层的方法包括在衬底上依次形成第一，第二和第三材料层。 第一，第二和第三材料层分别具有第一，第二和第三厚度。 在第一材料层内蚀刻开口，同时去除第三层的厚度的一部分或全部。 开口的深度与去除的第三材料层的厚度的比率对应于第一材料层和第二材料层的蚀刻选择性。 蚀刻操作可以自动终止以产生具有预定深度的开口。