公开(公告)号：US5895480A

公开(公告)日：1999-04-20

申请号：US541600

申请日：1995-10-10

Applicant: Wu Chi Yung ,  Kuo Cheng Yu

Inventor： Wu Chi Yung ,  Kuo Cheng Yu

IPC: G06F12/06

CPC classification number: G06F12/0661 ,  G11C8/12

Abstract: The present invention provides a method for accessing a memory device and a memory accessing device. The method includes a) providing the memory device having a plurality of memory sub-spaces respectively having a plurality of address ranges; b) respectively assigning a plurality of base addresses to the plurality of memory sub-spaces; c) inputting an access address; d) respectively operating the base addresses with the access address to obtain a plurality of operated results; and e) accessing one of the memory sub-spaces if a specific one of the operated results falls within one of the address ranges corresponding to the one memory sub-space. The memory accessing device includes an access address end, a data access end, an access selection end, a memory device having a plurality of memory sub-spaces, and a plurality of access devices respectively electrically connected to the memory sub-spaces, and each of which includes a base address storing device for storing therein a base address, an operating and comparing device for operating the access address with the base address to obtain an operated result and generating a data access enabling signal when the operated result falls within an address range, and a data buffer for accessing the respective memory sub-space in response to the data access enabling signal and the access selection signal.

Abstract translation: 本发明提供一种用于存取存储设备和存储器访问设备的方法。 该方法包括：a）提供具有分别具有多个地址范围的多个存储器子空间的存储器件; b）分别向多个存储器子空间分配多个基地址; c）输入访问地址; d）分别操作具有访问地址的基地址以获得多个操作结果; 以及e）如果所述操作结果中的特定一个落在与所述一个存储器子空间相对应的地址范围之一内，则访问所述存储器子空间中的一个。 存储器访问设备包括访问地址端，数据访问端，访问选择端，具有多个存储器子空间的存储设备和分别电连接到存储器子空间的多个访问设备，以及每个 其中包括用于在其中存储基地址的基地址存储装置，用于将访问地址与基地址进行操作以获得操作结果的操作和比较装置，并且当操作结果落在地址范围内时产生数据访问使能信号 以及用于响应于数据访问使能信号和访问选择信号而访问相应存储器子空间的数据缓冲器。

公开(公告)号：US5860155A

公开(公告)日：1999-01-12

申请号：US947445

申请日：1997-09-30

Applicant: Kuo Cheng Yu

Inventor： Kuo Cheng Yu

IPC: G06F9/30 ,  G06F9/35

CPC classification number: G06F9/35 ,  G06F9/30145

Abstract: The mechanism includes a virtual address detecting circuit for detecting the virtual address of the instruction code. When a virtual address is detected, an indicating signal is generated, which is then sent to an indirect address register to register the indirect address of the instruction code. Thereafter, an indirect address replacing circuit is used to decode and replace the indirect address registered in and sent from the indirect address register with a direct address. In the absence of the virtual address, the direct address is allowed to pass through the indirect address replacing circuit.

Abstract translation: 该机构包括用于检测指令代码的虚拟地址的虚拟地址检测电路。 当检测到虚拟地址时，产生指示信号，然后发送到间接地址寄存器以注册指令代码的间接地址。 此后，使用间接地址替换电路来解码和替换在间接地址寄存器中注册并且由直接地址发送的间接地址。 在没有虚拟地址的情况下，允许直接地址通过间接地址替换电路。

公开(公告)号：US5847587A

公开(公告)日：1998-12-08

申请号：US779430

申请日：1997-01-07

Applicant: Jason Chen ,  Yi Lin ,  Kuo-Cheng Yu

Inventor： Jason Chen ,  Yi Lin ,  Kuo-Cheng Yu

IPC: G01R19/165 ,  G06F1/28 ,  G06F1/30 ,  H03K17/22

CPC classification number: G06F1/30 ,  G01R19/16528 ,  G06F1/28

Abstract: A voltage detector circuit for instantaneously detecting abnormal voltages in a micro controller includes a voltage detection circuit connected between the power supply and reset voltage ends of an internal circuit of the micro controller so as to instantaneously detect changes in the power supply, without the time delay associated with the external low pass filter that supplies the reset voltage. The detecting circuit is a logic "NOT" gate which has a power supply connecting end connected to a reset voltage end of the internal circuit, an input end connected to the power supply end of the internal circuit, and an output end connected to a cooperating input end of the latch circuit, so that the latch circuit latches a signal output by the voltage detector whenever an abnormal power supply voltage is detected, and outputs a flag signal to the micro controller to effect an instantaneous reset of the micro controller. The latch may be a flip-flop, in which case one of the flip-flop inputs is connected to the voltage detector output and the other input may be connected together with the flip-flop power supply input to the reset voltage, the flip-flop providing two outputs, one of which may be connected to the micro controller reset pin, and the other of which may be connected to an interrupt or other indicator device.

Abstract translation: 用于瞬时检测微控制器中的异常电压的电压检测器电路包括连接在微控制器的内部电路的电源和复位电压端之间的电压检测电路，以便瞬时检测电源的变化，而不需要延时 与提供复位电压的外部低通滤波器相关联。 检测电路是逻辑“NOT”门，其具有连接到内部电路的复位电压端的电源连接端，连接到内部电路的电源端的输入端和连接到内部电路的输出端 锁存电路的输入端，使得当检测到异常电源电压时，锁存电路锁存由电压检测器输出的信号，并且向微控制器输出标志信号以实现微控制器的瞬时复位。 闩锁可以是触发器，在这种情况下，触发器输入中的一个连接到电压检测器输出，另一个输入可以与触发器电源输入连接到复位电压， 提供两个输出，其中一个可以连接到微控制器复位引脚，另一个可以连接到中断或其他指示器。

公开(公告)号：US5786717A

公开(公告)日：1998-07-28

申请号：US881909

申请日：1997-06-25

Applicant: Kuo Cheng Yu

Inventor： Kuo Cheng Yu

IPC: H03K17/22

CPC classification number: H03K17/22

Abstract: The present invention is related to a system reset device setting the reset status of a system in response to a reset signal. The system reset device according to the present invention includes a power-stability detecting circuit for detecting the stability of a power signal generated by a power source and provided for the system, an oscillation-stability detecting circuit for detecting the stability of an oscillation signal generated by an oscillator and provided for the system, and a level-control circuit electrically connected to the power-stability detecting circuit and the oscillation-stability detecting circuit for controlling a level state of the rest signal in response to the stability of the power signal and the oscillation signal. The level-control circuit includes an OR gate, an AND gate, and an S-R latch for performing the level state control of the reset signal.

Abstract translation: 本发明涉及一种系统复位装置，其响应复位信号设定系统的复位状态。 根据本发明的系统复位装置包括：功率稳定性检测电路，用于检测由电源产生并提供给系统的功率信号的稳定性;振荡稳定性检测电路，用于检测所产生的振荡信号的稳定性; 通过振荡器提供给系统，以及电平控制电路，其电连接到功率稳定性检测电路和振荡稳定性检测电路，用于响应于电力信号的稳定性来控制其余信号的电平状态，以及 振荡信号。 电平控制电路包括用于执行复位信号的电平状态控制的或门，与门和S-R锁存器。

公开(公告)号：US5770952A

公开(公告)日：1998-06-23

申请号：US489778

申请日：1995-06-13

Applicant: Kuo-Cheng Yu

Inventor： Kuo-Cheng Yu

IPC: H03K21/02 ,  H03K5/135

CPC classification number: H03K21/026

Abstract: A timer which provides both the surveying and counting functions. It contains a counter, a multiplexer, an edge-triggered controller, a time-base latching circuit, and a pulse-detecting circuit. It not only can be used as a timer, but can also be used as a counter to count the number of the external signals so as to detect the width of an external signal.

Abstract translation: 一个提供测量和计数功能的计时器。 它包含计数器，多路复用器，边沿触发控制器，时基锁存电路和脉冲检测电路。 它不仅可以用作定时器，还可以用作计数器来计数外部信号的数量，以便检测外部信号的宽度。

公开(公告)号：US5754806A

公开(公告)日：1998-05-19

申请号：US552217

申请日：1995-11-03

Applicant: Kuo Cheng Yu

Inventor： Kuo Cheng Yu

IPC: G06F9/26 ,  G06F9/30 ,  G06F9/312 ,  G06F9/38

CPC classification number: G06F9/3004 ,  G06F9/262 ,  G06F9/383

Abstract: A memory table look-up method for executing a table look-up instruction in an active program uses an instruction buffer executing device, a controller and a data register to output table look-up data from a memory to the data register. The method includes causing an instruction buffer executing device to execute a table look-up instruction obtained from the memory and pre-stored in the instruction buffer executing device in a first cycle to generate and output a table look-up signal, and to cause the controller to output a next instruction being an instruction next to the table look-up instruction in the active program from the memory to the instruction buffer executing device in response to the table look-up signal. The method further includes the step of causing the controller to generate a forbidding signal in a second cycle for latching the next instruction located in the instruction buffer executing device, and to generate and output a write-in instruction to the instruction buffer executing device for generating a write-in signal in order to output said table look-up data to the data register.

Abstract translation: 用于在活动程序中执行表查找指令的存储器表查找方法使用指令缓冲器执行装置，控制器和数据寄存器来将表查询数据从存储器输出到数据寄存器。 该方法包括使指令缓冲器执行装置执行从存储器获得并在第一周期中预先存储在指令缓冲执行装置中的表查找指令，以产生并输出表查找信号，并使 控制器，用于响应于表查找信号，从存储器向指令缓冲器执行装置输出下一条指令，该指令是与活动程序中的表查找指令相邻的指令。 该方法还包括使控制器在第二周期中产生禁止信号以锁存位于指令缓冲器执行装置中的下一个指令的步骤，并且生成并将写入指令输出到指令缓冲器执行装置，以产生 写入信号，以便将所述表查找数据输出到数据寄存器。

公开(公告)号：US20080174354A1

公开(公告)日：2008-07-24

申请号：US11757497

申请日：2007-06-04

Applicant: Kuo-Cheng Yu ,  Tyng-Yuan Luh

Inventor： Kuo-Cheng Yu ,  Tyng-Yuan Luh

IPC: G06F1/04

CPC classification number: G06F1/04

Abstract: A clock generating circuit and method therefor are provided, which includes a control unit, a first oscillating module, a second oscillating module, a status control unit, and a multiplexer. The control unit is used for outputting a first control signal and a second control signal so as to drive the first oscillating module and the second oscillating module to generate or stop from a first clock signal and a second signal to the multiplexer. The status control unit is used for judging whether the second clock signal approaches a stable state, for controlling the multiplexer to output selectively the first clock signal or the second clock signal so as to maintain the stable state of a clock outputting by the multiplexer for all the time

Abstract translation: 提供了一种时钟发生电路及其方法，其包括控制单元，第一振荡模块，第二振荡模块，状态控制单元和多路复用器。 控制单元用于输出第一控制信号和第二控制信号，以驱动第一振荡模块和第二振荡模块从第一时钟信号和第二信号产生或停止到多路复用器。 状态控制单元用于判断第二时钟信号是否接近稳定状态，用于控制多路复用器选择性地输出第一时钟信号或第二时钟信号，以便保持由多路复用器输出的时钟的稳定状态 时间

公开(公告)号：US5802071A

公开(公告)日：1998-09-01

申请号：US560311

申请日：1995-11-17

Applicant: I Liang Fang ,  Kuo Cheng Yu

Inventor： I Liang Fang ,  Kuo Cheng Yu

IPC: G06F11/22 ,  G06F11/267 ,  G01R31/28 ,  G06F11/00 ,  G11C29/00

CPC classification number: G06F11/2236 ,  G06F11/2273

Abstract: An improved micro-controller with a built-in test circuit is disclosed. It contains: (a) a test-mode switching register for receiving an external instruction from a test instrument so to select a test mode and to switch the external instruction to a predetermined circuit according to a selected test mode; (b) a test control circuit electrically connected to the test-mode switching register for controlling a timing of the external instruction received from the test instrument; (c) a multiplexer electrically connected to the test control circuit to receive an output signal from the test control circuit; (d) a control circuit electrically connected to the multiplexer for receiving an output signal therefrom, wherein the control circuit decodes and executes the output signal from the multiplexer, and sends an executing result to the test instrument; (e) a test program memory electrically connected to the multiplexer for storing a built-in test program, so as to allow the micro-controller to be tested in an internal mode; (f) an application program memory for storing an application program; and (g) a ROM read-out device electrically connected to the multiplexer and the application program memory for reading program codes from the application program memory to facilitate the test instrument to make a comparison.

Abstract translation: 公开了一种具有内置测试电路的改进的微控制器。 它包括：（a）测试模式切换寄存器，用于从测试仪器接收外部指令，以便根据所选择的测试模式选择测试模式并将外部指令切换到预定电路; （b）电连接到测试模式切换寄存器的测试控制电路，用于控制从测试仪器接收的外部指令的定时; （c）多路电路，电连接到测试控制电路以接收来自测试控制电路的输出信号; （d）电连接到多路复用器的控制电路，用于从其接收输出信号，其中控制电路解码并执行来自多路复用器的输出信号，并将执行结果发送给测试仪器; （e）电连接到所述多路复用器的测试程序存储器，用于存储内置测试程序，以允许所述微控制器以内部模式进行测试; （f）用于存储应用程序的应用程序存储器; 以及（g）电连接到多路复用器的ROM读出装置和应用程序存储器，用于从应用程序存储器读取程序代码，以便于测试仪器进行比较。

公开(公告)号：US5748948A

公开(公告)日：1998-05-05

申请号：US526850

申请日：1995-09-11

Applicant: Kuo-Cheng Yu ,  Bao-Shiang Sun ,  Ching-Yi Lin

Inventor： Kuo-Cheng Yu ,  Bao-Shiang Sun ,  Ching-Yi Lin

IPC: G06F1/24 ,  G06F11/00 ,  G06F1/04

CPC classification number: G06F11/0757 ,  G06F1/24

Abstract: The present invention relates to a reset signal generator adapted to be used with a microprocessor for generating a reset signal to initialize the microprocessor, which includes an oscillator to generate a fixed clock signal, a counter electrically connected to the oscillator for generating a cyclic signal in response to the fixed clock signal and outputting the reset signal at an end of a period of the cyclic signal, and a clear signal generating device electrically connected to the counter and outputting a clear signal for the counter in response to an output signal from the microprocessor. The present invention ensures that when the microprocessor is abnormal or down it will be initialized by the reset signal.

Abstract translation: 本发明涉及一种复位信号发生器，其适用于与微处理器一起产生复位信号以初始化微处理器，该微处理器包括产生固定时钟信号的振荡器，与振荡器电连接以产生循环信号的计数器 响应于固定时钟信号并在循环信号的周期结束时输出复位信号;以及清零信号发生装置，电连接到计数器，并响应于来自微处理器的输出信号输出计数器的清除信号 。 本发明确保当微处理器异常或下降时，它将被复位信号初始化。

公开(公告)号：US5737212A

公开(公告)日：1998-04-07

申请号：US567146

申请日：1995-12-04

Applicant: I Liang Fang ,  Kuo Cheng Yu ,  Jason Chen

Inventor： I Liang Fang ,  Kuo Cheng Yu ,  Jason Chen

IPC: G06F9/30 ,  G06F11/00 ,  G05B19/048

CPC classification number: G06F9/30083 ,  G06F11/0757 ,  G06F9/30076 ,  G06F9/30079

Abstract: A flag setting circuit for a microcontroller, which can be set with a HALT mode flag and a watchdog timer overflow flag by using a system power-on signal, an external reset signal, a watchdog timer overflow signal inside the microcontroller, a clear instruction for watchdog timer, a HALT mode instruction, and a wake-up signal. The setting circuit for the watchdog timer overflow flag includes a reset signal generator, a watchdog timer, a clear signal generator, a flag clear circuit, and a register circuit. The setting circuit for the HALT mode flag includes a HALT mode discerning circuit, a flag clear circuit, and a register circuit. The frequency source of the watchdog timer is provided by means of a frequency from the system oscillator divided with four, or by using a frequency of RC oscillator built in the system. Under the HALT mode, the RC oscillator is selected. By means of the HALT mode flag and the watchdog timer overflow flag, the operation condition of the system hardware can be discerned.

Abstract translation: 用于微控制器的标志设置电路，可以通过使用系统通电信号，外部复位信号，微控制器内部的看门狗定时器溢出信号，设置HALT模式标志和看门狗定时器溢出标志，清除指令 看门狗定时器，HALT模式指令和唤醒信号。 看门狗定时器溢出标志的设置电路包括复位信号发生器，看门狗定时器，清除信号发生器，标志清除电路和寄存器电路。 用于HALT模式标志的设置电路包括HALT模式识别电路，标志清除电路和寄存器电路。 看门狗定时器的频率源通过来自系统振荡器分频四个的频率，或通过使用内置于系统中的RC振荡器的频率来提供。 在HALT模式下，选择RC振荡器。 通过HALT模式标志和看门狗定时器溢出标志，可以看出系统硬件的运行状况。