公开(公告)号：US4604727A

公开(公告)日：1986-08-05

申请号：US528303

申请日：1983-08-31

申请人： Ashwin H. Shah ,  Pallab K. Chatterjee ,  James D. Gallia ,  Shivaling S. Mahant-Shetti

发明人： Ashwin H. Shah ,  Pallab K. Chatterjee ,  James D. Gallia ,  Shivaling S. Mahant-Shetti

IPC分类号： G11C11/417 ,  G06F11/10 ,  G06F12/14 ,  G06F13/28 ,  G06F13/42 ,  G11C7/00 ,  G11C7/24 ,  G11C11/34 ,  G11C11/401 ,  G11C11/41 ,  G11C11/413 ,  G11C29/00 ,  G11C29/42 ,  H01L21/822 ,  H01L27/04

CPC分类号： G06F12/1433 ,  G06F13/28 ,  G06F13/4243 ,  G11C7/24 ,  G06F11/10

摘要： A memory including various selectively configurable peripherals which provide on-chip low-level control features and a configuration RAM storing bits which both provide unclocked full logic-level outputs to control the selectively configurable peripherals and can also be accessed and read out. That is, each cell in the configuration RAM has two output modes: a digital continuous output, which is provided as a continuous control signal to various peripheral circuits and a selectable analog output which is used to read the information stored in the configuration RAM.

摘要翻译： 包括提供片上低级控制特征的各种选择性可配置的外围设备的存储器和存储位的配置RAM，它们都提供非锁定的全逻辑电平输出以控制可选择性地配置的外围设备，并且还可被访问和读出。 也就是说，配置RAM中的每个单元具有两种输出模式：作为连续控制信号提供给各种外围电路的数字连续输出和用于读取存储在配置RAM中的信息的可选择的模拟输出。

公开(公告)号：US07262468B2

公开(公告)日：2007-08-28

申请号：US10035606

申请日：2001-12-28

申请人： James D. Gallia ,  Srikanth Krishnan ,  Anand T. Krishnan

发明人： James D. Gallia ,  Srikanth Krishnan ,  Anand T. Krishnan

IPC分类号： H01L23/62 ,  H01L27/01 ,  H01L27/02 ,  H01L31/0392

CPC分类号： H01L27/1203

摘要： According to one embodiment of the invention, a silicon-on-insulator device includes an insulative layer formed overlying a substrate and a source and drain region formed overlying the insulative layer. The source region and the drain region comprise a material having a first conductivity type. A body region is disposed between the source region and the drain region and overlying the insulative layer. The body region comprises a material having a second conductivity type. A gate insulative layer overlies the body region. This device also includes a gate region overlying the gate insulative layer. The device also includes a diode circuit conductively coupled to the source region and a conductive connection coupling the gate region to the diode circuit.

摘要翻译： 根据本发明的一个实施例，绝缘体上硅器件包括覆盖在衬底上的绝缘层和形成在绝缘层上的源极和漏极区。 源区和漏区包括具有第一导电类型的材料。 体区域设置在源极区域和漏极区域之间并且覆盖绝缘层。 身体区域包括具有第二导电类型的材料。 门绝缘层覆盖身体区域。 该器件还包括覆盖栅极绝缘层的栅极区域。 该器件还包括一个二极管电路，该二极管电路与该源极区域导电耦合，一个将该栅极区域耦合到该二极管电路的导电连接。

公开(公告)号：US4601019A

公开(公告)日：1986-07-15

申请号：US528209

申请日：1983-08-31

申请人： Ashwin H. Shah ,  James D. Gallia ,  I-Fay Wang ,  Shivaling S. Mahant-Shetti

发明人： Ashwin H. Shah ,  James D. Gallia ,  I-Fay Wang ,  Shivaling S. Mahant-Shetti

IPC分类号： G11C11/413 ,  G11C29/00 ,  G11C29/04 ,  G11C13/00

CPC分类号： G11C29/808

摘要： A byte-wide memory with column redundancy. The redundant columns can each be substituted for any column in the half-array, without regard to which bit position the defective column relates to. Fuses store the address information of the defective columns, and when a match between the externally received column address and the stored defective-column-address is found, the sense amplifier for the bit position which contains that defective column is disabled, and the output of the redundant column (selected by whichever word line is activated) is multiplexed into the I-O buss. Thus, before the row address signal has even been decoded, the defective column has been disabled and one of the redundant columns has effectively been substituted. This configuration means that it is not necessary to have one redundant column for every bit position, but each redundant column can substitute for a defective column in any bit position, and more than one defective column in a single bit position can each be replaced.

摘要翻译： 具有列冗余的字节宽的内存。 冗余列可以分别代替半数组中的任何列，而不考虑缺陷列与哪个位的关系。 保险丝存储有缺陷列的地址信息，当外部接收的列地址与存储的故障列地址之间的匹配被找到时，包含该缺陷列的位位置的读出放大器被禁止，并且输出 冗余列（由哪个字线被激活选择）被复用到IO总线中。 因此，在行地址信号甚至被解码之前，有缺陷的列已经被禁用，并且冗余列之一被有效地替代。 该配置意味着对于每个位位置不需要具有一个冗余列，但是每个冗余列可以替代任何位位置中的有缺陷的列，并且可以替换单个位位置中的多于一个的有缺陷的列。

公开(公告)号：US5107147A

公开(公告)日：1992-04-21

申请号：US677001

申请日：1991-03-28

申请人： Ah-Lyan Yee ,  James D. Gallia

发明人： Ah-Lyan Yee ,  James D. Gallia

IPC分类号： H01L27/118 ,  H03K19/0944 ,  H03K19/173

CPC分类号： H03K19/09448 ,  H01L27/11896 ,  H03K19/1735

摘要： A BiCMOS gate array base is disclosed which is capable of simultaneously implementing a BiCMOS gate and/or a multitude of CMOS gates. The cell has symmetry about 1 axis, with the bipolar devices in the center and equally accessible for interconnect by two CMOS sections. The cell allows half-cell macro circuit blocks to be placed into the base cell in an independent and flexible fashion. The same macro can be placed in either CMOS section because of the mirror symmetry. The base cell can be divided into 2 units of macro placement. The number of devices in the CMOS section is variable. This cell architecture can be extended to other mixed technologies.

摘要翻译： 公开了能够同时实现BiCMOS门和/或多个CMOS门的BiCMOS门阵列基极。 该单元具有约1轴的对称性，双极器件位于中心，并且可通过两个CMOS部分互连。 该单元允许以独立和灵活的方式将半单元宏电路块放入基本单元。 由于镜像对称，相同的宏可以放置在CMOS部分中。 基本单元可以分为2个单元的宏位置。 CMOS部分中的器件数量是可变的。 这种单元架构可以扩展到其他混合技术。

公开(公告)号：US06563158B1

公开(公告)日：2003-05-13

申请号：US10039810

申请日：2001-11-16

申请人： Theodore W. Houston ,  James D. Gallia

发明人： Theodore W. Houston ,  James D. Gallia

IPC分类号： H01L27108

CPC分类号： H01L27/0629 ,  H01L27/10894

摘要： An integrated circuit includes several circuit portions coupled between two rails that carry respective different voltage potentials. Each circuit portion includes a relatively small capacitance, coupled in series with a resistance which is sufficient to effect substantial limiting of the magnitude of any leakage current that may flow through the capacitor.

摘要翻译： 集成电路包括耦合在两个轨道之间的几个电路部分，其承载相应的不同电压电位。 每个电路部分包括相对较小的电容，其与电阻串联，该电阻足以实现可能流过电容器的任何漏电流的大小的大幅度限制。

公开(公告)号：US5173623A

公开(公告)日：1992-12-22

申请号：US842801

申请日：1992-02-27

申请人： Kwok K. Chau ,  James D. Gallia ,  Ashwin H. Shah

发明人： Kwok K. Chau ,  James D. Gallia ,  Ashwin H. Shah

IPC分类号： H03K19/00 ,  H03K19/0944

CPC分类号： H03K19/0008 ,  H03K19/09448

摘要： BiCMOS circuits are disclosed which achieve high speed operation under a wide range of loading conditions. The circuits are capable of providing a full output voltage swing and dissipate virtually no static power. The BiCMOS circuits are implemented using both CMOS and bipolar transistors. The circuits use their output signal to control the CMOS transistors that overcome bipolar output drops for full swing operation. The same fundamental CMOS and bipolar configurations can be applied to implement complex and simple logic functions such as NAND, NOR, AND, or OR operations.

摘要翻译： 公开了BiCMOS电路，其在宽范围的负载条件下实现高速运行。 这些电路能够提供完整的输出电压摆幅并实际上消散静态功率。 BiCMOS电路使用CMOS和双极晶体管实现。 这些电路使用它们的输出信号来控制克服双极性输出下降以用于全速操作的CMOS晶体管。 可以应用相同的基本CMOS和双极配置来实现复杂和简单的逻辑功能，例如NAND，NOR，AND或OR操作。

公开(公告)号：US5019888A

公开(公告)日：1991-05-28

申请号：US76622

申请日：1987-07-23

申请人： David B. Scott ,  Patrick W. Bosshart ,  James D. Gallia

发明人： David B. Scott ,  Patrick W. Bosshart ,  James D. Gallia

IPC分类号： H01L27/02

CPC分类号： H01L27/0251

摘要： An output buffer (26) comprises a plurality of transistors (28) arranged in parallel between an output pin (34) and ground (38). Resistors (30) are connected in series between the drain (30) of the transistors (28) and the output pin (34) to ensure that an electrostatic discharge generated through normal handling will be distributed substantially equally through each of the transistors (28), thus preventing damage to the output buffer (26).

摘要翻译： 输出缓冲器（26）包括并排布置在输出引脚（34）和接地（38）之间的多个晶体管（28）。 电阻器（30）串联连接在晶体管（28）的漏极（30）和输出引脚（34）之间，以确保通过正常处理产生的静电放电将基本上相等地分布通过每个晶体管（28）， ，从而防止对输出缓冲器（26）的损坏。

公开(公告)号：US07638412B2

公开(公告)日：2009-12-29

申请号：US11782523

申请日：2007-07-24

申请人： James D. Gallia ,  Srikanth Krishnan ,  Anand T. Krishnan

发明人： James D. Gallia ,  Srikanth Krishnan ,  Anand T. Krishnan

IPC分类号： H01L21/20 ,  H01L21/36 ,  H01L21/302 ,  H01L21/461

CPC分类号： H01L27/1203

摘要： According to one embodiment of the invention, a silicon-on-insulator device includes an insulative layer formed overlying a substrate and a source and drain region formed overlying the insulative layer. The source region and the drain region comprise a material having a first conductivity type. A body region is disposed between the source region and the drain region and overlying the insulative layer. The body region comprises a material having a second conductivity type. A gate insulative layer overlies the body region. This device also includes a gate region overlying the gate insulative layer. The device also includes a diode circuit conductively coupled to the source region and a conductive connection coupling the gate region to the diode circuit.

摘要翻译： 根据本发明的一个实施例，绝缘体上硅器件包括覆盖在衬底上的绝缘层和形成在绝缘层上的源极和漏极区。 源区和漏区包括具有第一导电类型的材料。 体区域设置在源极区域和漏极区域之间并且覆盖绝缘层。 身体区域包括具有第二导电类型的材料。 门绝缘层覆盖身体区域。 该器件还包括覆盖栅极绝缘层的栅极区域。 该器件还包括一个二极管电路，该二极管电路与该源极区域导电耦合，以及一个将栅极区域耦合到该二极管电路的导电连接。

公开(公告)号：US06708303B1

公开(公告)日：2004-03-16

申请号：US09259004

申请日：1999-02-26

申请人： James D. Gallia

发明人： James D. Gallia

IPC分类号： G01R3128

CPC分类号： G01R31/318541 ,  G01R31/318536 ,  G01R31/318575

摘要： A scan circuit (10) has a scan data input (17), a normal data input (18), a clock input (22), a scan enable input (19), a normal data output (23), and a scan data output (24). The scan circuit includes a multiplexer (27) having two data inputs respectively coupled to the scan data input and normal data input of the scan circuit, having a control input coupled to the scan enable input of the scan circuit, and having an output. The scan circuit also includes a D-type flip-flop (28) having a data input coupled to the output of the multiplexer, having a clock input coupled to the clock input of the scan circuit, and having a data output serving as the normal data output of the scan circuit. The scan circuit further includes a gate (29) having a first input coupled to an output of the flip-flop, having a second input coupled to the scan enable input of the scan circuit, and having an output which serves as the scan data output of the scan circuit.

摘要翻译： 扫描电路（10）具有扫描数据输入（17），正常数据输入（18），时钟输入（22），扫描使能输入（19），正常数据输出（23）和扫描数据 输出（24）。 扫描电路包括具有分别耦合到扫描数据输入和扫描电路的正常数据输入的两个数据输入的多路复用器（27），其具有耦合到扫描电路的扫描使能输入并具有输出的控制输入。 扫描电路还包括具有耦合到多路复用器的输出的数据输入的D型触发器（28），具有耦合到扫描电路的时钟输入的时钟输入，并具有用作正常的数据输出 扫描电路的数据输出。 扫描电路还包括具有耦合到触发器的输出的第一输入的栅极（29），其具有耦合到扫描电路的扫描使能输入的第二输入，并且具有用作扫描数据输出的输出 的扫描电路。

公开(公告)号：US5126973A

公开(公告)日：1992-06-30

申请号：US479510

申请日：1990-02-14

申请人： James D. Gallia ,  Jim Childers

发明人： James D. Gallia ,  Jim Childers

IPC分类号： G11C29/00

CPC分类号： G11C29/808

摘要： A redundancy scheme for a memory device, as well as a method for developing a redundancy scheme, resulting in improved repairability for given space constraints. A memory device is formed with a plurality of data blocks having individual input/output paths. Each block comprises an array of memory cells arranged in addressable rows and columns along row lines and column lines. The array is configured in sub-blocks each comprising a plurality of the memory cells. The device includes row address circuitry for selecting a row of the memory cells, column address circuitry for selecting a column of the memory cells and address repair circuitry. The address repair circuitry is configurable to render a first portion of a first of the columns of cells responsive to the address of a portion of a second of the columns of cells. There is also provided a method for eliminating a defect in a memory device having a logical data block formed with addressable rows and columns of memory cells. A defect associated with a first column of cells is eliminated by programming a portion of a second column of cells to be responsive to the addresses of a portion of the cells in the first column.