公开(公告)号：US20240282607A1

公开(公告)日：2024-08-22

申请号：US18200201

申请日：2023-05-22

Applicant: Kyu Ok LEE ,  SAMSUNG ELECTRONICS CO., LTD.

Inventor： Kyu Ok LEE ,  Ji Yong KIM

IPC: H01L21/67 ,  H01L21/677 ,  H01L21/68

CPC classification number: H01L21/67259 ,  H01L21/67778 ,  H01L21/681

Abstract: The present invention relates to a position determination apparatus for a robot detection laser sensor system in front-opening unified pods (FOUPs), including: an external server; and a wafer processing device for performing processing for wafers and transmitting integration management data to the external server, wherein the wafer processing device may include: the FOUPs configured to accommodate the wafers therein; loadports to which the FOUPs are detachably coupled; processing chambers in which the processing for the wafers are performed; and an equipment front end module (EFEM) disposed between the processing chambers and the loadports and having an end-effector adapted to get the wafers out of the FOUPs into the processing chambers or put the wafers finished in processing in the processing chambers into the FOUPs.

公开(公告)号：US08415720B2

公开(公告)日：2013-04-09

申请号：US13172036

申请日：2011-06-29

Applicant: Badih El-Kareh ,  Kyu Ok Lee ,  Joo Hyung Kim ,  Jung Joo Kim

Inventor： Badih El-Kareh ,  Kyu Ok Lee ,  Joo Hyung Kim ,  Jung Joo Kim

IPC: H01L29/66

CPC classification number: H01L29/66901 ,  H01L29/8086

Abstract: A vertical junction field-effect transistor in a CMOS base-technology. The vertical junction field-effect transistor includes a semiconductor substrate having a source region and a drain region, a main-channel region formed between the source region and the drain region, a well region formed on the main-channel region between the source region and the drain region, vertical pinch-off regions formed at both source and drain ends or only on the source-end of the well region on the main-channel region in the source region and the drain region respectively, a source contact on the vertical pinch-off region in the source region, a drain contact on the vertical pinch-off region in the drain region, a gate contact on the well region between the source contact and the drain contact and shallow trench isolations formed on the well region.

Abstract translation: CMOS基础技术中的垂直结型场效应晶体管。 垂直结场效应晶体管包括具有源极区和漏极区的半导体衬底，形成在源区和漏区之间的主沟道区，形成在源极区和源极区之间的主沟道区上的阱区， 在源极区域和漏极区域的主沟道区域上分别形成在源极和漏极端部处或仅在阱区域的源极端处的垂直夹断区域，垂直夹点处的源极接触 源极区域中的漏极区域，漏极区域中的垂直夹断区域上的漏极接触，源极接触和漏极接触之间的阱区域上的栅极接触以及在阱区域上形成的浅沟槽隔离。

公开(公告)号：US07824985B2

公开(公告)日：2010-11-02

申请号：US12344497

申请日：2008-12-27

Applicant: Kyu-Ok Lee

Inventor： Kyu-Ok Lee

IPC: H01L21/336

CPC classification number: H01L29/7813 ,  H01L29/0865 ,  H01L29/0878 ,  H01L29/1095 ,  H01L29/41766 ,  H01L29/66727 ,  H01L29/66734 ,  H01L29/7811

Abstract: A method of manufacturing a recessed gate transistor includes forming a hard mask pattern over a substrate; and then forming a trench in the substrate by performing an etching process using the hard mask pattern as an etch mask; and then performing a pullback-etching process on the hard mask pattern to expose a source region in the substrate; and then forming a gate silicon layer in the trench and over the substrate including the hard mask pattern after performing the pullback-etching process; and then performing an etch-back process on the gate silicon layer to expose the hard mask pattern such that the uppermost surface of the gate silicon layer is below the uppermost surface of the hard mask pattern; and then removing the hard mask pattern; and then simultaneously etching the gate silicon layer and the exposed portion of the substrate.

Abstract translation: 一种制造凹陷栅极晶体管的方法，包括在衬底上形成硬掩膜图案; 然后通过使用硬掩模图案作为蚀刻掩模进行蚀刻工艺在衬底中形成沟槽; 然后对所述硬掩模图案进行拉回蚀刻处理，以暴露所述基板中的源极区域; 然后在进行拉回蚀刻工艺之后在沟槽中和在包括硬掩模图案的衬底上形成栅极硅层; 然后在栅极硅层上进行回蚀处理以暴露硬掩模图案，使得栅极硅层的最上表面在硬掩模图案的最上表面之下; 然后去除硬掩模图案; 然后同时蚀刻栅极硅层和衬底的暴露部分。

公开(公告)号：US20210252717A1

公开(公告)日：2021-08-19

申请号：US17306859

申请日：2021-05-03

Applicant: Kyu Ok LEE

Inventor： Kyu Ok LEE ,  Jin Hee LIM

IPC: B25J13/08 ,  B25J11/00 ,  B25J9/16

Abstract: Provided are an end effect measuring module and an end effect monitoring apparatus using the same. The end effect measuring module is installed at through holes formed between an Equipment Front End Module (EFEM) equipped with an end effector and a semiconductor processing apparatus for processing a wafer and measuring the position according to the movement path of a target passing the through holes. The measurement target is the end effector, and a sensing unit measures whether or not the end effector is shifted and changed in direction. A light receiving unit of the sensing unit outputs an electrical signal that is higher or lower than a reference value in response to shifting of the end effector, or outputs an electrical signal increasing or decreasing along a time axis in response to a directional change of the end effector.

公开(公告)号：US20090197380A1

公开(公告)日：2009-08-06

申请号：US12344497

申请日：2008-12-27

Applicant: Kyu-Ok Lee

Inventor： Kyu-Ok Lee

IPC: H01L21/336

CPC classification number: H01L29/7813 ,  H01L29/0865 ,  H01L29/0878 ,  H01L29/1095 ,  H01L29/41766 ,  H01L29/66727 ,  H01L29/66734 ,  H01L29/7811

Abstract: A method of manufacturing a recessed gate transistor includes forming a hard mask pattern over a substrate; and then forming a trench in the substrate by performing an etching process using the hard mask pattern as an etch mask; and then performing a pullback-etching process on the hard mask pattern to expose a source region in the substrate; and then forming a gate silicon layer in the trench and over the substrate including the hard mask pattern after performing the pullback-etching process; and then performing an etch-back process on the gate silicon layer to expose the hard mask pattern such that the uppermost surface of the gate silicon layer is below the uppermost surface of the hard mask pattern; and then removing the hard mask pattern; and then simultaneously etching the gate silicon layer and the exposed portion of the substrate.

Abstract translation: 一种制造凹陷栅极晶体管的方法，包括在衬底上形成硬掩膜图案; 然后通过使用硬掩模图案作为蚀刻掩模进行蚀刻工艺在衬底中形成沟槽; 然后对所述硬掩模图案进行拉回蚀刻处理，以暴露所述基板中的源极区域; 然后在进行拉回蚀刻工艺之后在沟槽中和在包括硬掩模图案的衬底上形成栅极硅层; 然后在栅极硅层上进行回蚀处理以暴露硬掩模图案，使得栅极硅层的最上表面在硬掩模图案的最上表面之下; 然后去除硬掩模图案; 然后同时蚀刻栅极硅层和衬底的暴露部分。

公开(公告)号：US11772278B2

公开(公告)日：2023-10-03

申请号：US17306859

申请日：2021-05-03

Applicant: Kyu Ok Lee

Inventor： Kyu Ok Lee ,  Jin Hee Lim

IPC: H01L21/67 ,  B25J13/08 ,  B25J9/16 ,  B25J11/00

CPC classification number: B25J13/088 ,  B25J9/1664 ,  B25J11/0095 ,  B25J13/087

Abstract: Provided are an end effect measuring module and an end effect monitoring apparatus using the same. The end effect measuring module is installed at through holes formed between an Equipment Front End Module (EFEM) equipped with an end effector and a semiconductor processing apparatus for processing a wafer and measuring the position according to the movement path of a target passing the through holes. The measurement target is the end effector, and a sensing unit measures whether or not the end effector is shifted and changed in direction. A light receiving unit of the sensing unit outputs an electrical signal that is higher or lower than a reference value in response to shifting of the end effector, or outputs an electrical signal increasing or decreasing along a time axis in response to a directional change of the end effector.

公开(公告)号：US20130001656A1

公开(公告)日：2013-01-03

申请号：US13172036

申请日：2011-06-29

Applicant: BADIH EL-KAREH ,  Kyu Ok LEE ,  Joo Hyung KIM ,  Jung Joo KIM

Inventor： BADIH EL-KAREH ,  Kyu Ok LEE ,  Joo Hyung KIM ,  Jung Joo KIM

IPC: H01L29/76

CPC classification number: H01L29/66901 ,  H01L29/8086

Abstract: A vertical junction field-effect transistor in a CMOS base-technology. The vertical junction field-effect transistor includes a semiconductor substrate having a source region and a drain region, a main-channel region formed between the source region and the drain region, a well region formed on the main-channel region between the source region and the drain region, vertical pinch-off regions formed at both source and drain ends or only on the source-end of the well region on the main-channel region in the source region and the drain region respectively, a source contact on the vertical pinch-off region in the source region, a drain contact on the vertical pinch-off region in the drain region, a gate contact on the well region between the source contact and the drain contact and shallow trench isolations formed on the well region.

Abstract translation: CMOS基础技术中的垂直结型场效应晶体管。 垂直结场效应晶体管包括具有源极区和漏极区的半导体衬底，形成在源区和漏区之间的主沟道区，形成在源极区和源极区之间的主沟道区上的阱区， 在源极区域和漏极区域的主沟道区域上分别形成在源极和漏极端部处或仅在阱区域的源极端处的垂直夹断区域，垂直夹点处的源极接触 源极区域中的漏极区域，漏极区域中的垂直夹断区域上的漏极接触，源极接触和漏极接触之间的阱区域上的栅极接触以及在阱区域上形成的浅沟槽隔离。

公开(公告)号：US20120032303A1

公开(公告)日：2012-02-09

申请号：US12916311

申请日：2010-10-29

Applicant: Badih ELKAREH ,  Kyu Ok LEE ,  Sang Yong LEE

Inventor： Badih ELKAREH ,  Kyu Ok LEE ,  Sang Yong LEE

IPC: H01L29/73 ,  H01L21/331

CPC classification number: H01L29/7322 ,  H01L29/0692 ,  H01L29/0821 ,  H01L29/41708 ,  H01L29/66272

Abstract: The present invention relates to semiconductor technologies, and more particularly to a bipolar junction transistor (BJT) in a CMOS base technology and methods of forming the same. The BJT includes a semiconductor substrate having an emitter region, a base having a first contact, and a collector having a second contact and a well plug; a first silicide film on the first contact; a second silicide film on the second contact; a first silicide blocking layer on or over the semiconductor substrate between the first and second silicide films, and a second silicide blocking layer on the semiconductor substrate between the first silicide film and the emitter region.

Abstract translation: 本发明涉及半导体技术，更具体地涉及CMOS基底技术中的双极结型晶体管（BJT）及其形成方法。 BJT包括具有发射极区域的半导体衬底，具有第一触点的基底和具有第二触点和阱插塞的集电极; 第一接触处的第一硅化物膜; 第二接触层上的第二硅化物膜; 在第一和第二硅化物膜之间或之上半导体衬底上的第一硅化物阻挡层，以及在第一硅化物膜和发射极区之间的半导体衬底上的第二硅化物阻挡层。

公开(公告)号：US20240429082A1

公开(公告)日：2024-12-26

申请号：US18703734

申请日：2022-10-05

Applicant: Kyu Ok LEE ,  SAMSUNG ELECTRONICS CO., LTD.

Inventor： Kyu Ok LEE ,  Ji Yong KIM

IPC: H01L21/677 ,  H01L21/67 ,  H01L21/68

Abstract: A FOUP comprises: an external server; and a substrate processing device for performing substrate processing and transmitting integrated management data to the external server. The substrate processing device comprises: FOUPs for accommodating a plurality of substrates; load ports to which the FOUPs are detachably coupled; a process chamber in which substrate processing is performed; an EFEM, which is provided between the process chamber and the load ports, and has an end effector for getting, into the process chamber, the substrates accommodated in the FOUPs or putting, into the FOUPs, the substrates for which processing is completed in the process chamber; and a control unit for transmitting, if the FOUPs are loaded in the load ports, moving path data of the end effector to the external server when the end effector enters into or retreats from the FOUPs.