Process for fabricating intrinsic layer and applications
    1.
    发明授权
    Process for fabricating intrinsic layer and applications 失效
    制造本征层和应用的工艺

    公开(公告)号:US5733815A

    公开(公告)日:1998-03-31

    申请号:US341545

    申请日:1994-11-18

    摘要: A method of simultaneously forming a gallium arsenide p-i-n structure having p, i, and n regions, which includes heating to dissolve gallium arsenide in a solvent such as bismuth or gallium to form a saturated solution of gallium arsenide in the solvent, contacting the solution with a gaseous mixture, which mixture includes hydrogen, water vapor and products of reactions between the hydrogen and the water vapor with the solvent and with silicon dioxide, to form a contacted solution, coating a suitably selected substrate, such as a group III-V compound such as gallium arsenide, with the contacted solution, cooling the coated substrate to precipitate gallium arsenide from the contacted solution onto the substrate, and removing the substrate coated with a layer of gallium arsenide having a p-i-n structure which constitutes the product having an i region dopant concentration of less than about 10.sup.12 cm.sup.-3.

    摘要翻译: PCT No.PCT / US93 / 04782 Sec。 371日期:1994年11月18日 102(e)1994年11月18日日期PCT提交1993年5月20日PCT公布。 公开号WO93 / 24954 日期1993年12月9日一种同时形成具有p,i和n区域的砷化镓pin结构的方法,其包括加热以溶解诸如铋或镓的溶剂中的砷化镓,以在溶剂中形成砷化镓的饱和溶液 将溶液与气体混合物接触,该混合物包括氢气,水蒸气以及在与溶剂和二氧化硅之间的氢气和水蒸汽之间的反应产物,以形成接触的溶液,涂覆适当选择的基底,例如 III-V族化合物如砷化镓与所述接触溶液一起冷却所述涂覆的基底以将砷化镓从所述接触溶液沉淀到所述基底上,以及除去涂覆有构成所述产物的pin结构的砷化镓层的基底 具有小于约1012cm-3的i区掺杂浓度。

    Method for making high-voltage high-speed gallium arsenide power
Schottky diode
    2.
    发明授权
    Method for making high-voltage high-speed gallium arsenide power Schottky diode 失效
    制造高压高速砷化镓电源肖特基二极管的方法

    公开(公告)号:US5622877A

    公开(公告)日:1997-04-22

    申请号:US326893

    申请日:1994-10-21

    CPC分类号: H01L29/66212 H01L29/872

    摘要: A power GaAs Schottky diode with a chemically deposited Ni barrier having a reverse breakdown voltage of 140 V, a forward voltage drop at 50 A/cm.sup.2 of 0.7 V at 23.degree. C., 0.5 V at 150.degree. C. and 0.3 V at 250.degree. C. and having a reverse leakage current density at -50 V of 0.1 .mu.A/cm.sup.2 at 23.degree. C. and 1 mA/cm.sup.2 at 150.degree. C. The high-voltage high-speed power Schottky semiconductor device is made by chemically depositing a nickel barrier electrode on a semiconductor which includes gallium arsenide and then etching the device to create side portions which are treated and protected to create the Schottky device.

    摘要翻译: 具有化学沉积的Ni屏障的功率GaAs肖特基二极管具有140V的反向击穿电压,在50℃下在50A / cm 2下的正向压降为0.7V,在23℃下为0.7V,在150℃为0.5V,在250℃为0.3V 在-50℃时的反向泄漏电流密度为0.1μA/ cm 2,在23℃和150mA时为1mA / cm 2。高电压高速功率肖特基半导体器件通过化学 在包括砷化镓的半导体上沉积镍阻挡电极,然后蚀刻该器件以产生经过处理和保护以产生肖特基器件的侧部。

    Controlled semiconductor capacitors
    3.
    发明授权
    Controlled semiconductor capacitors 失效
    受控半导体电容器

    公开(公告)号:US5680073A

    公开(公告)日:1997-10-21

    申请号:US381973

    申请日:1995-02-06

    CPC分类号: H01L29/93 H01L27/1443

    摘要: A controlled capacitor system, which includes a capacitor element (C1) and a forward-biased diode element (D2) connected in series with the capacitor element (C1). The system is such that the diode element (D2) has a capacitance which is less than the capacitance of the capacitance of the capacitor element (C1) when the diode element (D2) is under zero bias. The capacitance of the diode element (D2) is controlled by varying the forward current (I2) through the diode (D2). The forward current (I2) acting to control the capacitance of the diode element is selected such that the capacitance of the diode element (D2) is smaller than the capacitance of the capacitor element (C1) when the current (I2) through the diode element (D2) is below a minimum value. The capacitance of the diode element (D2) is bigger than the capacitance of the capacitor element (C1) when the current (I2) through the diode element (D2) exceeds a maximum value.

    摘要翻译: PCT No.PCT / US94 / 06144 Sec。 371日期:1995年2月6日 102(e)日期1995年2月6日PCT 1994年5月31日PCT PCT。 公开号WO94 / 29960 日期1994年12月22日一种可控电容器系统,其包括与电容器元件(C1)串联连接的电容器元件(C1)和正向偏置二极管元件(D2)。 该系统使得当二极管元件(D2)处于零偏压时,二极管元件(D2)的电容小于电容器元件(C1)的电容的电容。 通过改变通过二极管(D2)的正向电流(I2)来控制二极管元件(D2)的电容。 选择用于控制二极管元件的电容的正向电流(I2),使得当通过二极管元件的电流(I2)时,二极管元件(D2)的电容小于电容器元件(C1)的电容 (D2)低于最小值。 当通过二极管元件(D2)的电流(I2)超过最大值时,二极管元件(D2)的电容大于电容器元件(C1)的电容。