BRIDGING AND INTEGRATING DEVICES ACROSS PROCESSING SYSTEMS
    2.
    发明申请
    BRIDGING AND INTEGRATING DEVICES ACROSS PROCESSING SYSTEMS 审中-公开
    跨越处理系统的桥接和集成设备

    公开(公告)号:US20140250253A1

    公开(公告)日:2014-09-04

    申请号:US13977010

    申请日:2012-10-03

    IPC分类号: G06F12/10 G06F13/40 G06F13/32

    摘要: Particular embodiments described herein can offer an electronic fabric for a processing system that includes a fabric adapter to couple to a first fabric associated with a first system and to couple to a second fabric associated with a second system. The fabric adapter is configured to pass bidirectional communications between the first system and the second system. The electronic fabric can further include an address translation agent configured to map a first physical address in a first address space of the first system to a second physical address in a second address space of the second system.

    摘要翻译: 本文描述的特定实施例可以提供用于处理系统的电子结构,其包括织物适配器以耦合到与第一系统相关联的第一织物并且耦合到与第二系统相关联的第二织物。 结构适配器被配置为在第一系统和第二系统之间传递双向通信。 电子结构还可以包括地址转换代理,被配置为将第一系统的第一地址空间中的第一物理地址映射到第二系统的第二地址空间中的第二物理地址。

    Bacteria removing cleaner
    3.
    发明授权
    Bacteria removing cleaner 失效
    除菌清洁剂

    公开(公告)号:US06681411B1

    公开(公告)日:2004-01-27

    申请号:US10201820

    申请日:2002-07-25

    IPC分类号: E03D908

    CPC分类号: E03D9/08

    摘要: A bacteria removing cleaner comprises a water-stopping control unit and a nozzle means. A plurality of conduits are used for transferring water. The water-stopping control unit has a rotary switch, a main body and a water-stop control valve for controlling the water inlet and water stopping. The main body is spaced into a water outlet space and a water inlet space. A water-stop control valve is installed at the interface of the water inlet space and the water outlet space. The top end of the water-stop control valve is connected to the rotary switch. The water-stop control valve is utilized to control water flow. By rotating a rotary switch, a washing time can be controlled effectively. Moreover, the bacteria removing cleaner is capable of being assembled to a stool rapidly and quickly. Thereby, the lifetime is prolonged.

    摘要翻译: 除菌清洁器包括止水控制单元和喷嘴装置。 多个导管用于输送水。 停水控制单元具有用于控制进水和停水的旋转开关,主体和停水控制阀。 主体间隔开一个出水口和一个进水空间。 在进水口和出水口的接口处安装止水控制阀。 停水控制阀的顶端连接到旋转开关。 停水控制阀用于控制水流量。 通过旋转旋转开关,可以有效地控制洗涤时间。 此外,细菌去除清洁剂能够快速且快速地组装到粪便中。 从而延长使用寿命。

    Hybrid nanotube/CMOS dynamically reconfigurable architecture and system therefore
    4.
    发明授权
    Hybrid nanotube/CMOS dynamically reconfigurable architecture and system therefore 有权
    混合纳米管/ CMOS动态可重构架构和系统

    公开(公告)号:US09099195B2

    公开(公告)日:2015-08-04

    申请号:US13314155

    申请日:2011-12-07

    摘要: A hybrid nanotube, high-performance, dynamically reconfigurable architecture, NATURE, is provided, and a design optimization flow method and system, NanoMap. A run-time reconfigurable architecture is provided by associating a non-volatile universal memory to each logic element to enable cycle-by-cycle reconfiguration and logic folding, while remaining CMOS compatible. Through logic folding, significant logic density improvement and flexibility in performing area-delay tradeoffs are possible. NanoMap incorporates temporal logic folding during the logic mapping, temporal clustering and placement steps. NanoMap provides for automatic selection of a best folding level, and uses force-direct scheduling to balance resources across folding stages. Mapping can thereby target various optimization objectives and user constraints. A high-density, high-speed carbon nanotube RAM can be implemented as the universal memory, allowing on-chip multi-context configuration storage, enabling fine-grain temporal logic folding, and providing a significant increase in relative logic density.

    摘要翻译: 提供混合纳米管,高性能,动态可重构架构,NATURE,以及NanoMap的设计优化流程方法和系统。 通过将非易失性通用存储器与每个逻辑元件相关联来提供运行时可重构架构,以实现逐周期重新配置和逻辑折叠,同时保持CMOS兼容性。 通过逻辑折叠,可以实现显着的逻辑密度改进和执行区域延迟权衡的灵活性。 NanoMap在逻辑映射,时间聚类和放置步骤期间包含时间逻辑折叠。 NanoMap提供自动选择最佳折叠级别,并使用强制直接调度来平衡折叠阶段的资源。 因此,映射可以针对各种优化目标和用户约束。 高密度高速碳纳米管RAM可以实现为通用存储器,允许片上多上下文配置存储,实现细粒度时间逻辑折叠,并提供相对逻辑密度的显着增加。

    HYBRID NANOTUBE/CMOS DYNAMICALLY RECONFIGURABLE ARCHITECTURE AND AN INTEGRATED DESIGN OPTIMIZATION METHOD AND SYSTEM THEREFOR
    5.
    发明申请
    HYBRID NANOTUBE/CMOS DYNAMICALLY RECONFIGURABLE ARCHITECTURE AND AN INTEGRATED DESIGN OPTIMIZATION METHOD AND SYSTEM THEREFOR 有权
    HYBRID NANOTUBE / CMOS动态可重构架构及其集成设计优化方法及其系统

    公开(公告)号:US20090219051A1

    公开(公告)日:2009-09-03

    申请号:US12297638

    申请日:2007-04-19

    摘要: A hybrid nanotube, high-performance, dynamically reconfigurable architecture, NATURE, is provided, and a design optimization flow method and system, NanoMap. A run-time reconfigurable architecture is provided by associating a non-volatile universal memory to each logic element to enable cycle-by-cycle reconfiguration and logic folding, while remaining CMOS compatible. Through logic folding, significant logic density improvement and flexibility in performing area-delay tradeoffs are possible. NanoMap incorporates temporal logic folding during the logic mapping, temporal clustering and placement steps. NanoMap provides for automatic selection of a best folding level, and uses force-direct scheduling to balance resources across folding stages. Mapping can thereby target various optimization objectives and user constraints. A high-density, high-speed carbon nanotube RAM can be implemented as the universal memory, allowing on-chip multi-context configuration storage, enabling fine-grain temporal logic folding, and providing a significant increase in relative logic density.

    摘要翻译: 提供混合纳米管,高性能,动态可重构架构,NATURE,以及NanoMap的设计优化流程方法和系统。 通过将非易失性通用存储器与每个逻辑元件相关联来提供运行时可重构架构,以实现逐周期重新配置和逻辑折叠,同时保持CMOS兼容性。 通过逻辑折叠,可以实现显着的逻辑密度改进和执行区域延迟权衡的灵活性。 NanoMap在逻辑映射,时间聚类和放置步骤期间包含时间逻辑折叠。 NanoMap提供自动选择最佳折叠级别,并使用强制直接调度来平衡折叠阶段的资源。 因此,映射可以针对各种优化目标和用户约束。 高密度高速碳纳米管RAM可以实现为通用存储器,允许片上多上下文配置存储,实现细粒度时间逻辑折叠,并提供相对逻辑密度的显着增加。

    Faucet head
    7.
    外观设计

    公开(公告)号:USD954176S1

    公开(公告)日:2022-06-07

    申请号:US29784306

    申请日:2021-05-19

    申请人: Li Shang

    设计人: Li Shang

    Shaping data packet traffic
    8.
    发明授权
    Shaping data packet traffic 有权
    整形数据包流量

    公开(公告)号:US09420532B2

    公开(公告)日:2016-08-16

    申请号:US13976110

    申请日:2011-12-29

    IPC分类号: H04W52/02

    摘要: According to some embodiments, a communication module 120 may be configured to transmit data packet traffic and a management module 110 may be configured to shape the data packet traffic transmitted by the communication module 120. The management module 110 may shape the data packet traffic by buffering data packets routed at different times to the communication module 120 based on at least one power management factor.

    摘要翻译: 根据一些实施例,通信模块120可以被配置为传输数据分组业务,并且管理模块110可以被配置成对由通信模块120发送的数据分组流量进行整形。管理模块110可以通过缓冲来形成数据分组业务 基于至少一个电源管理因素在不同时间路由到通信模块120的数据分组。

    SHAPING DATA PACKET TRAFFIC
    9.
    发明申请
    SHAPING DATA PACKET TRAFFIC 有权
    形成数据包交通

    公开(公告)号:US20140029500A1

    公开(公告)日:2014-01-30

    申请号:US13976110

    申请日:2011-12-29

    IPC分类号: H04W52/02

    摘要: According to some embodiments, a communication module 120 may be configured to transmit data packet traffic and a management module 110 may be configured to shape the data packet traffic transmitted by the communication module 120. The management module 110 may shape the data packet traffic by buffering data packets routed at different times to the communication module 120 based on at least one power management factor.

    摘要翻译: 根据一些实施例,通信模块120可以被配置为传输数据分组业务,并且管理模块110可以被配置成对由通信模块120发送的数据分组流量进行整形。管理模块110可以通过缓冲来形成数据分组业务 基于至少一个电源管理因素在不同时间路由到通信模块120的数据分组。

    METHOD AND SYSTEM FOR A RUN-TIME RECONFIGURABLE COMPUTER ARCHITECTURE
    10.
    发明申请
    METHOD AND SYSTEM FOR A RUN-TIME RECONFIGURABLE COMPUTER ARCHITECTURE 有权
    运行时可重构计算机架构的方法和系统

    公开(公告)号:US20130135008A1

    公开(公告)日:2013-05-30

    申请号:US13513277

    申请日:2010-12-01

    IPC分类号: G06F17/50 H03K19/177

    摘要: A reconfigurable computer architecture is disclosed. The reconfigurable computer architecture has a plurality of logic elements, a plurality of connection switching elements, and a plurality of volatile and/or non-volatile configuration random access memories (RAMs). Each of the configuration RAMs is electrically coupled to at least one of the plurality of logic elements or at least one of the connection switching elements.

    摘要翻译: 公开了一种可重构计算机体系结构。 可重构计算机体系结构具有多个逻辑元件,多个连接切换元件以及多个易失性和/或非易失性配置随机存取存储器(RAM)。 每个配置RAM电耦合到多个逻辑元件中的至少一个或连接切换元件中的至少一个。