Planar lightwave circuit waveguide bends and beamsplitters
    1.
    发明授权
    Planar lightwave circuit waveguide bends and beamsplitters 有权
    平面光波电路波导弯管和分束器

    公开(公告)号:US07206470B2

    公开(公告)日:2007-04-17

    申请号:US10973068

    申请日:2004-10-25

    IPC分类号: G02B6/12 G02B6/26 G02B6/42

    CPC分类号: G02B6/126

    摘要: A planar lightwave circuit has a waveguide having a bend and plurality of multiple trenches with parallel front and back interfaces. The trench and waveguide refractive indexes are different such that a refractive interface is defined between the waveguide and the trench. The trench may include a material of higher refractive index than the waveguide, such as silicon, or alternatively a material having a lower refractive index than the waveguide, such as an air void. The trench is disposed on the waveguide bend such that the front and back planar interfaces have an angle of incidence to a direction of the lightwave propagation from the waveguide. The invention also includes beamsplitters that include trenches that reflect a portion of a lightwave in a first direction and a portion of a lightwave in a second direction.

    摘要翻译: 平面光波电路具有具有弯曲的波导和多个具有平行的前后接口的多个沟槽。 沟槽和波导折射率是不同的,使得在波导和沟槽之间限定折射界面。 沟槽可以包括比诸如硅的波导更高的折射率的材料,或者替代地具有比波导低折射率的材料,例如空气空隙。 沟槽设置在波导弯管上,使得前和后平面界面具有与波导从光波传播的方向的入射角。 本发明还包括分束器,其包括在第一方向上反射光波的一部分并且沿第二方向反射光波的一部分的沟槽。

    Simplified process flow for CMOS fabrication
    2.
    发明授权
    Simplified process flow for CMOS fabrication 有权
    CMOS制造简化工艺流程

    公开(公告)号:US06235565B1

    公开(公告)日:2001-05-22

    申请号:US09392855

    申请日:1999-09-09

    申请人: Lixia Li

    发明人: Lixia Li

    IPC分类号: H01L218238

    摘要: A method of fabricating a semiconductor device wherein there is provided a semiconductor substrate of a first conductivity type. A dopant is implanted in one region of the substrate of opposite conductivity type and that region is masked, preferably with a silicon oxide mask. A relatively heavy dose of a dopant of the first conductivity type is implanted in a different region of the substrate while retaining the mask on the region of the substrate doped with dopant of the opposite conductivity type. The two implants are driven farther into the substrate to form a first tank of said first conductivity type and a second tank of opposite conductivity type by an annealing step while retaining the mask on the region of the substrate doped with dopant of the opposite conductivity type. A second implant of the first conductivity type is then implanted into the tank of first conductivity type while retaining the mask on the region of the substrate doped with dopant of the opposite conductivity type. Fabrication of the device is then completed in standard manner except that there is no Vtn, pattern and there are no Vtn implants. The second implant of the first conductivity type has a lower dosage then the prior implant of first conductivity type. The higher dosage implant of the first conductivity type is provided to set the depth of the tank and is from about 6×1012/cm2 to about 1.9×1013/cm2. The lower dosage implant of the first conductivity type is from about 1×1012/cm2 to about 8×1012/cm2.

    摘要翻译: 一种制造半导体器件的方法,其中提供了第一导电类型的半导体衬底。 将掺杂剂注入到具有相反导电类型的衬底的一个区域中,并且该区域被掩蔽,优选地使用氧化硅掩模。 将相对大量的第一导电类型的掺杂剂注入到衬底的不同区域中,同时将掩模保持在掺杂有相反导电类型的掺杂剂的衬底的区域上。 通过退火步骤将两个植入物进一步驱动到衬底中以形成具有所述第一导电类型的第一罐和具有相反导电类型的第二罐,同时将掩模保持在掺杂有相反导电类型的掺杂剂的衬底的区域上。 然后将第一导电类型的第二植入物注入到第一导电类型的槽中,同时将掩模保持在掺杂有相反导电类型的掺杂剂的衬底的区域上。 然后以标准方式完成装置的制造,除了没有Vtn,图案和没有Vtn植入物。 第一种导电类型的第二植入物具有较低的剂量,然后是先前的第一导电类型的植入。 提供第一导电类型的较高剂量植入物以设定罐的深度,并且为约6×10 12 / cm 2至约1.9×10 13 / cm 2。 第一导电类型的较低剂量植入物为约1×10 12 / cm 2至约8×10 12 / cm 2。

    Packaging implementation while mitigating threshold voltage shifting
    4.
    发明申请
    Packaging implementation while mitigating threshold voltage shifting 审中-公开
    包装实施,同时减轻阈值电压偏移

    公开(公告)号:US20080157291A1

    公开(公告)日:2008-07-03

    申请号:US11657206

    申请日:2007-01-24

    申请人: Lixia Li He Lin

    发明人: Lixia Li He Lin

    IPC分类号: H01L23/58 H01L21/31

    摘要: One or more passivation layers are added to the end of a semiconductor process flow to provide additional protection for devices (e.g., transistors) formed during the process. An additional layer is then formed and/or an anneal is performed to mitigate threshold voltage shifting that may be induced by the passivation layers. Mitigation of threshold voltage shifting increases the life expectancy of devices (e.g., transistors) formed during the process, which in turn mitigates yield loss by facilitating predictable or otherwise desirable behavior of the devices (e.g., transistors).

    摘要翻译: 将一个或多个钝化层添加到半导体工艺流程的末端,以为在工艺期间形成的器件(例如,晶体管)提供额外的保护。 然后形成附加层和/或执行退火以减轻可能由钝化层引起的阈值电压偏移。 阈值电压偏移的减轻增加了在该过程期间形成的器件(例如,晶体管)的寿命,其又通过促进器件(例如,晶体管)的可预测或其它期望的行为来减轻产量损失。

    Method and system to dynamically compensate for probe tip misalignement when testing integrated circuits
    5.
    发明授权
    Method and system to dynamically compensate for probe tip misalignement when testing integrated circuits 有权
    检测集成电路时动态补偿探头尖端误差的方法和系统

    公开(公告)号:US07629805B2

    公开(公告)日:2009-12-08

    申请号:US12051300

    申请日:2008-03-19

    申请人: Lixia Li

    发明人: Lixia Li

    IPC分类号: G01R31/02 G01K5/00 H01K3/10

    CPC分类号: G01R31/2891 Y10T29/49155

    摘要: Method for dynamically compensating probe tip misalignment with a semiconductor wafer. The wafer is located on a handler and the wafer is adjusted to a first temperature. Probe tips of an inspection system are moved to a first position centered above pads of a test module on the wafer. The first position is recorded in a memory of the inspection system at the first temperature. The wafer and the probe tips are adjusted to a second temperature while the wafer remains in the inspection system. A second position of the probe tips is recorded in the memory while the probe tips and the wafer are equilibrated at the second temperature. A difference between the first and second position is calculated. Relative positions of the probe tips or the wafer is compensated based on the calculated difference, such that the probe tips are re-centered above the pads at the second temperature.

    摘要翻译: 用于动态补偿与半导体晶片的探针针尖不对准的方法。 晶片位于处理器上,并将晶片调节至第一温度。 检查系统的探针尖端移动到位于晶片上的测试模块的焊盘上方的第一位置。 第一位置在第一温度下被记录在检查系统的存储器中。 将晶片和探针尖端调节到第二温度,同时晶片保留在检查系统中。 探针尖端的第二位置记录在存储器中,同时探针尖端和晶片在第二温度下平衡。 计算第一和第二位置之间的差异。 基于计算出的差异来补偿探针尖端或晶片的相对位置,使得探针尖端在第二温度下在衬垫上重新居中。

    METHOD AND SYSTEM TO DYNAMICALLY COMPENSATE FOR PROBE TIP MISALIGNEMENT WHEN TESTING INTEGRATED CIRCUITS
    6.
    发明申请
    METHOD AND SYSTEM TO DYNAMICALLY COMPENSATE FOR PROBE TIP MISALIGNEMENT WHEN TESTING INTEGRATED CIRCUITS 有权
    检测集成电路时动态补偿探测误差的方法和系统

    公开(公告)号:US20090239316A1

    公开(公告)日:2009-09-24

    申请号:US12051300

    申请日:2008-03-19

    申请人: Lixia Li

    发明人: Lixia Li

    IPC分类号: H01L21/66 G01R31/26

    CPC分类号: G01R31/2891 Y10T29/49155

    摘要: Method for dynamically compensating probe tip misalignment with a semiconductor wafer. The wafer is located on a handler and the wafer is adjusted to a first temperature. Probe tips of an inspection system are moved to a first position centered above pads of a test module on the wafer. The first position is recorded in a memory of the inspection system at the first temperature. The wafer and the probe tips are adjusted to a second temperature while the wafer remains in the inspection system. A second position of the probe tips is recorded in the memory while the probe tips and the wafer are equilibrated at the second temperature. A difference between the first and second position is calculated. Relative positions of the probe tips or the wafer is compensated based on the calculated difference, such that the probe tips are re-centered above the pads at the second temperature.

    摘要翻译: 用于动态补偿与半导体晶片的探针针尖不对准的方法。 晶片位于处理器上,并将晶片调节至第一温度。 检查系统的探针尖端移动到位于晶片上的测试模块的焊盘上方的第一位置。 第一位置在第一温度下被记录在检查系统的存储器中。 将晶片和探针尖端调节到第二温度,同时晶片保留在检查系统中。 探针尖端的第二位置记录在存储器中,同时探针尖端和晶片在第二温度下平衡。 计算第一和第二位置之间的差异。 基于计算出的差异来补偿探针尖端或晶片的相对位置,使得探针尖端在第二温度下在衬垫上重新居中。

    Planar lightwave circuit waveguide bends and beamsplitters
    7.
    发明申请
    Planar lightwave circuit waveguide bends and beamsplitters 有权
    平面光波电路波导弯管和分束器

    公开(公告)号:US20050152633A1

    公开(公告)日:2005-07-14

    申请号:US10973068

    申请日:2004-10-25

    IPC分类号: G02B6/126 G02B6/12

    CPC分类号: G02B6/126

    摘要: A planar lightwave circuit has a waveguide having a bend and plurality of multiple trenches with parallel front and back interfaces. The trench and waveguide refractive indexes are different such that a refractive interface is defined between the waveguide and the trench. The trench may include a material of higher refractive index than the waveguide, such as silicon, or alternatively a material having a lower refractive index than the waveguide, such as an air void. The trench is disposed on the waveguide bend such that the front and back planar interfaces have an angle of incidence to a direction of the lightwave propagation from the waveguide. The invention also includes beamsplitters that include trenches that reflect a portion of a lightwave in a first direction and a portion of a lightwave in a second direction.

    摘要翻译: 平面光波电路具有具有弯曲的波导和多个具有平行的前后接口的多个沟槽。 沟槽和波导折射率是不同的,使得在波导和沟槽之间限定折射界面。 沟槽可以包括比诸如硅的波导更高的折射率的材料,或者替代地具有比波导低折射率的材料,例如空气空隙。 沟槽设置在波导弯管上,使得前和后平面界面具有与波导从光波传播的方向的入射角。 本发明还包括分束器,其包括在第一方向上反射光波的一部分并且沿第二方向反射光波的一部分的沟槽。