公开(公告)号：US5414380A

公开(公告)日：1995-05-09

申请号：US47895

申请日：1993-04-19

申请人： Jeffery A. Floyd ,  Lloyd P. Matthews

发明人： Jeffery A. Floyd ,  Lloyd P. Matthews

IPC分类号： G06F3/00 ,  G06F1/22 ,  H03K17/30 ,  H03K19/173 ,  H03K19/003

CPC分类号： G06F1/22 ,  H03K19/1732

摘要： An integrated circuit (20) configures the active level of an input, output, or input/output pin by sensing a logic state on the pin's bonding pad (21) at the inactivation of a reset signal, such as a power-on reset signal. The integrated circuit (20) selects a true or complement signal to provide to or from an internal circuit (25). The voltage level on the pin is latched on the active-to-inactive transition of the power-on reset signal. Thus, the use of proper board-level termination resistors (70, 71) programs the pins to the desired active logic level without the need for additional logic circuitry or a dedicated device pin.

摘要翻译： 集成电路（20）通过在激活复位信号（例如上电复位信号）时感测引脚的焊盘（21）上的逻辑状态来配置输入，输出或输入/输出引脚的有效电平 。 集成电路（20）选择用于提供给内部电路（25）的真或互补信号。 引脚上的电压电平在上电复位信号的有效到无效转换时被锁存。 因此，使用适当的电路板级终端电阻（70,71）将引脚编程到所需的有源逻辑电平，而不需要额外的逻辑电路或专用器件引脚。

公开(公告)号：US4996450A

公开(公告)日：1991-02-26

申请号：US486443

申请日：1990-02-28

申请人： Lloyd P. Matthews

发明人： Lloyd P. Matthews

IPC分类号： H03K19/003

CPC分类号： H03K19/00315 ,  H03K19/00361

摘要： In a data processing system having an ALU and a memory, a decode/driver circuit has a dynamic node in which the voltage variation of the node is controlled. When the circuit is enabled, the dynamic node is precharged to a predetermined voltage potential which drives an output drive transistor. The output drive transistor couples a decoded select signal to an output terminal and inadvertently causes the dynamic node's voltage potential to change, thereby negatively affecting the voltage at the output terminal. To compensate, a transistor is provided which connects a predetermined voltage terminal to the dynamic node in response to the voltage at the output terminal.

摘要翻译： 在具有ALU和存储器的数据处理系统中，解码/驱动器电路具有控制节点的电压变化的动态节点。 当电路被使能时，动态节点被预充电到驱动输出驱动晶体管的预定电压电位。 输出驱动晶体管将解码的选择信号耦合到输出端子，并且无意中导致动态节点的电压电位改变，从而不利地影响输出端子处的电压。 为了补偿，提供了一个晶体管，其响应于输出端子处的电压将预定电压端子连接到动态节点。

公开(公告)号：US06646844B1

公开(公告)日：2003-11-11

申请号：US09461909

申请日：1999-12-15

申请人： Lloyd P. Matthews

发明人： Lloyd P. Matthews

IPC分类号： H02H326

CPC分类号： G06F1/28

摘要： A module for controlling an output signal in a system including first and second power supply signals. The module includes a comparator coupled to receive the first power supply signal and a second signal and coupled to provide a control signal. Also included is a pad module coupled to receive the first power supply signal and the control signal and coupled to provide an output signal. The output signal of the pad module is disabled when the control signal has a first value. Various aspects of the present invention may also be realized through a power-on disable module for an apparatus having multiple power supply signals. The power-on disable module includes a controller coupled to receive a plurality of power supply signals and coupled to provide a power-on disable signal depending on a comparison of the power supply signals.

摘要翻译： 一种用于控制包括第一和第二电源信号的系统中的输出信号的模块。 模块包括耦合以接收第一电源信号和第二信号并被耦合以提供控制信号的比较器。 还包括焊盘模块，其被耦合以接收第一电源信号和控制信号并被耦合以提供输出信号。 当控制信号具有第一值时，焊盘模块的输出信号被禁止。 本发明的各个方面也可以通过具有多个电源信号的装置的上电禁止模块来实现。 上电禁用模块包括耦合以接收多个电源信号并被耦合以根据电源信号的比较来提供上电禁止信号的控制器。

公开(公告)号：US5691554A

公开(公告)日：1997-11-25

申请号：US573094

申请日：1995-12-15

申请人： Lloyd P. Matthews

发明人： Lloyd P. Matthews

IPC分类号： H01L27/02 ,  H01L29/76

CPC分类号： H01L27/0255

摘要： A protection circuit (13) for an integrated circuit (10) is capable of handling higher externally-provided voltages supplied to internal circuitry within the integrated circuit (10). The protection circuit (13) comprises a zener diode (20), wherein a N+ type diffusion region (38) is separated from a P field implant (40) lying between the N+ type diffusion region (38) and a P+ type diffusion region (39).

摘要翻译： 用于集成电路（10）的保护电路（13）能够处理提供给集成电路（10）内的内部电路的较高的外部提供的电压。 保护电路（13）包括齐纳二极管（20），其中N +型扩散区域（38）与位于N +型扩散区域（38）和P +型扩散区域之间的P场注入（40）分离 39）。

公开(公告)号：US07215150B2

公开(公告)日：2007-05-08

申请号：US11047427

申请日：2005-01-31

申请人： Cynthia A. Torres ,  Lloyd P. Matthews

发明人： Cynthia A. Torres ,  Lloyd P. Matthews

IPC分类号： H03K19/0175 ,  H03K3/00

CPC分类号： H03K19/018585 ,  H03K19/00384 ,  H03K19/018592

摘要： A circuit implements a method to adjust input/output (I/O) characteristics of an I/O pad circuit (10) depending upon which value of an I/O supply voltage is used within a range of supply voltages. An I/O supply voltage being supplied to the pad circuit is detected by detecting (18, 20) its value relative to a known reference (16). Portions of the I/O pad circuit are selectively enabled in response to the detected I/O supply voltage. By selecting the ratio of P-channel and N-channel transistors, physical characteristics of the circuit are controlled. Examples of the controlled physical characteristics include slew rate, signal rise and fall times, and duty cycle control which is controlled by forcing all rising and falling edges to have a midpoint at the same point in time. Therefore a same I/O pad circuit may be optimally used in numerous applications regardless of the supply voltage value.

摘要翻译： 电路实现了根据在电源电压范围内使用I / O电源电压的值来调整I / O焊盘电路（10）的输入/输出（I / O）特性的方法。 通过相对于已知参考（16）检测（18,20）其值来检测提供给焊盘电路的I / O电源电压。 响应于检测到的I / O电源电压，I / O焊盘电路的部分被选择性地使能。 通过选择P沟道和N沟道晶体管的比例，控制电路的物理特性。 受控物理特性的示例包括压摆率，信号上升和下降时间，以及通过强制所有上升沿和下降沿在相同时间点具有中点来控制的占空比控制。 因此，无论电源电压值如何，在许多应用中可以最佳地使用相同的I / O焊盘电路。

公开(公告)号：US06674304B1

公开(公告)日：2004-01-06

申请号：US09258378

申请日：1999-02-26

申请人： Lloyd P. Matthews

发明人： Lloyd P. Matthews

IPC分类号： H03K190175

CPC分类号： H03K17/167

摘要： An output buffer (100) contains a low voltage driver (110), a medium voltage driver (108), and a high voltage driver (106). When an output pad (112) is configured to operate between ground and the medium voltage, the low voltage driver (110) is first used during low-to-high transitions to drive the output pad (112) from ground to an intermediate voltage in a fast manner. After the intermediate voltage is obtained on the output pad (112), a detection circuit (111) will switch output pad control from the low voltage driver (110) to the medium voltage driver (108). The medium voltage driver (108) will drive the output pad (112) from the intermediate voltage to the final logic one output voltage. This two-stage low-to-high driving methodology ensures that there will be less delay time from input (DO) to the output pad (112). In addition, the drivers (108) and (110) contain protection transistors (228), (231), and (266) that allow programming on reset to be accomplished in an error free manner through use of the output pad (112) as an input during reset operations.

摘要翻译： 输出缓冲器（100）包含低电压驱动器（110），中压驱动器（108）和高压驱动器（106）。 当输出焊盘（112）被配置为在接地和中等电压之间工作时，低电压驱动器（110）首先在低到高的转变期间被使用以将输出焊盘（112）从地驱动到中间电压 快速的方式 在输出焊盘（112）上获得中间电压之后，检测电路（111）将输出焊盘控制从低电压驱动器（110）切换到中压驱动器（108）。 中压驱动器（108）将驱动输出焊盘（112）从中间电压到最终的逻辑1输出电压。 这种两级低到高的驾驶方法确保从输入（DO）到输出垫（112）的延迟时间将更少。 此外，驱动器（108）和（110）包含保护晶体管（228），（231）和（266），其允许以无错误的方式通过使用输出焊盘（112）来实现复位上的编程，如 复位操作期间的输入。

公开(公告)号：US4920320A

公开(公告)日：1990-04-24

申请号：US285997

申请日：1988-12-19

申请人： Lloyd P. Matthews

发明人： Lloyd P. Matthews

IPC分类号： H03L7/107 ,  H03L7/183

CPC分类号： H03L7/107 ,  H03L7/183

摘要： A phase locked loop has a digital phase comparator, a filter with multiple bandwidths, a voltage controlled oscillator and a frequency divider connected to the phase comparator to complete the loop. Control circuitry is coupled to both the phase comparator and filter for controlling switching between a wide bandwidth and a narrow bandwidth. The switching in bandwidth is in response to either detecting when the output signal is within a predetermined range of the reference frequency for a predetermined time period or detecting when the output signal exceeds and falls below the reference frequency a predetermined number of times. The control circuit is implemented with circuitry which accurately detects either condition and is capable of blocking any premature change of bandwidth.

摘要翻译： 锁相环具有数字相位比较器，具有多个带宽的滤波器，压控振荡器和连接到相位比较器的分频器以完成该环路。 控制电路耦合到相位比较器和滤波器两者，用于控制宽带宽和窄带宽之间的切换。 带宽切换响应于在预定时间段内检测输出信号是否在参考频率的预定范围内，或者检测何时输出信号超过并且低于参考频率预定次数。 控制电路由电路实现，其精确地检测任一条件并且能够阻止任何过早的带宽变化。