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    DEVICE AND METHODS FOR RECONFIGURABLE ANALOG INPUT MONITORING
    1.
    发明申请
    DEVICE AND METHODS FOR RECONFIGURABLE ANALOG INPUT MONITORING 有权

    公开(公告)号：US20250158629A1

    公开(公告)日：2025-05-15

    申请号：US18440552

    申请日：2024-02-13

    Applicant: Microchip Technology Incorporated

    Inventor： Thomas Youbok Lee ,  Ibiyemi Omole ,  Jimmy Yu ,  Santosh Patel ,  Daniel Meacham ,  Hadj Attlassy

    IPC: H03M1/12

    Abstract: An ADC system may include an ADC, a comparator, a voltage source, a comparator output polarity control circuit and a comparator output counter. An analog input signal may be input to a first input of the comparator, and an output of the voltage source may be input to a second input of the comparator. The comparator may generate an output to the comparator output polarity control circuit, and the comparator output counter may count clock cycles while the comparator output is asserted and may assert a monitor output based on the comparator output counter value. The monitor output may be an interrupt, an alarm or other system alerts and may control system operation.

    Scalable common view time transfer and related apparatuses and methods
    2.
    发明授权
    Scalable common view time transfer and related apparatuses and methods 有权

    公开(公告)号：US12298414B2

    公开(公告)日：2025-05-13

    申请号：US18511689

    申请日：2023-11-16

    Applicant: Microchip Technology Incorporated

    Inventor： George Zampetti

    IPC: G01S19/25 ,  G01S19/23 ,  G01S19/39

    Abstract: Common view time transfer and related apparatuses and methods are disclosed. An apparatus includes a receiver oscillator to provide a local clock signal and one or more processors. The one or more processors are to perform, at least partially based on the local clock signal, event time tagging pre-processing at least partially responsive to satellite signals received from one or more satellites to generate a decimated precision correction state estimate; determine, per satellite signal pseudo range residuals; determine a navigation engine clock state; perform a precision clock state pre-processing operation at least partially responsive to the navigation engine clock state and the decimated precision correction state estimate to generate a precision navigation clock state; and generate a common view real time report at least partially responsive to the per satellite signal pseudo range residuals and the precision navigation clock state.

    METHODS AND APPARATUSES FOR CONTROLLING TRANSMIT POWER LEVEL ACCORDING TO PREAMBLE BIT LENGTH
    3.
    发明申请
    METHODS AND APPARATUSES FOR CONTROLLING TRANSMIT POWER LEVEL ACCORDING TO PREAMBLE BIT LENGTH 有权

    公开(公告)号：US20250142612A1

    公开(公告)日：2025-05-01

    申请号：US18929350

    申请日：2024-10-28

    Applicant: Microchip Technology Incorporated

    Inventor： Yifeng Yang

    IPC: H04W72/542

    Abstract: In one example, a method of a transceiver comprises receiving a first communication signal including a first message; detecting a signal strength of the first communication signal; generating a preamble having a preamble bit length that is adjusted at least partially based on the detected signal strength of the first communication signal; and transmitting a second communication signal including a second message, the second message including the preamble having the preamble bit length.

    PULSE WIDTH MODULATION CIRCUIT TO GENERATE A FEEDBACK CLOCK
    4.
    发明申请
    PULSE WIDTH MODULATION CIRCUIT TO GENERATE A FEEDBACK CLOCK 有权

    公开(公告)号：US20250132765A1

    公开(公告)日：2025-04-24

    申请号：US18923751

    申请日：2024-10-23

    Applicant: Microchip Technology Incorporated

    Inventor： Keith Curtis

    IPC: H03L7/099 ,  H03K5/156 ,  H03L7/093 ,  H03L7/18

    Abstract: A device may have a reference divider circuit to divide a reference clock, a phase-frequency detector circuit to detect a detected phase difference and a detected frequency difference based on the reference divider output and a feedback clock, a loop filter circuit to filter the detector output, a voltage controlled oscillator (VCO) control output pin coupled to the loop filter output, a VCO clock divider control output pin to select a divisor of an external clock divider circuit, a divided VCO clock input pin for coupling to an output of the external clock divider circuit, a pulse-width modulation (PWM) circuit having a PWM clock input coupled to the divided VCO clock input pin, a period register to store a period value, a duty cycle register to store a duty cycle value and a pulse-width modulated output based on the period value and the duty cycle value.

    POLYHEDRON MODELS AND METHODS USING COMPUTATIONAL OPERATIONS FOR DISTRIBUTING DATA
    9.
    发明申请
    POLYHEDRON MODELS AND METHODS USING COMPUTATIONAL OPERATIONS FOR DISTRIBUTING DATA 有权

    公开(公告)号：US20250068331A1

    公开(公告)日：2025-02-27

    申请号：US18394226

    申请日：2023-12-22

    Applicant: Microchip Technology Incorporated

    Inventor： Anand Nagarajan

    IPC: G06F3/06

    Abstract: Methods based on polyhedron models using computational operations for distributing data and parities among different data storage media. Devices, systems, and methods that split data into data strips, wherein the number of data strips equals the number of vertices of a polyhedron and respective ones of the number of the data strips correspond to respective ones of the number of vertices of the polyhedron; construct a number of parities, wherein the number of parities equals the number of faces of the polyhedron and respective ones of the number of parities correspond to respective ones of the number of parities of the polyhedron, wherein respective ones of the number of parities are constructed by computationally operating the data strips corresponding to vertices respectively associated with a face of the polyhedron corresponding to the respective parity; and distribute subsets of data strips and subsets of parities to subsets of storage media.

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