公开(公告)号：US20100172187A1

公开(公告)日：2010-07-08

申请号：US12349417

申请日：2009-01-06

申请人： Mohan Vamsi Dunga ,  Man Mui ,  Masaaki Higashitani

发明人： Mohan Vamsi Dunga ,  Man Mui ,  Masaaki Higashitani

IPC分类号： G11C16/06 ,  G11C7/00 ,  G11C7/06

CPC分类号： G11C11/5642 ,  G11C16/26

摘要： A sense amplifier is disclosed. One embodiment is a sensing circuit that includes a sensing device and a sense transistor coupled to the sensing device. A first switch that is coupled to the sense transistor and to the sensing device causes the sensing device to be charged to a first voltage that is a function of the threshold voltage of the sense transistor. One or more second switches that are coupled to the sensing device and to a target element. The second switches couple the sensing device to the target element to modify the first voltage on the sensing device and decouple the target element from the sensing device during a sense phase in which the modified first voltage is applied to the sense transistor. A condition of the target element is determined based on whether or not the sense transistor turns on in response to applying the modified first voltage to the sense transistor.

摘要翻译： 公开了一种读出放大器。 一个实施例是感测电路，其包括耦合到感测装置的感测装置和感测晶体管。 耦合到感测晶体管和感测装置的第一开关使得感测装置被充电到作为感测晶体管的阈值电压的函数的第一电压。 耦合到感测装置和目标元件的一个或多个第二开关。 第二开关将感测装置耦合到目标元件以修改感测装置上的第一电压，并且在将修改的第一电压施加到感测晶体管的感测阶段期间将目标元件与感测装置分离。 目标元件的条件基于响应于将修改的第一电压施加到感测晶体管是否导通而确定。

公开(公告)号：US20090080265A1

公开(公告)日：2009-03-26

申请号：US11861571

申请日：2007-09-26

申请人： Nima Mokhlesi ,  Dengtao Zhao ,  Man Mui ,  Hao Nguyen ,  Seungpil Lee ,  Deepak Chandra Sekar ,  Tapan Samaddar

发明人： Nima Mokhlesi ,  Dengtao Zhao ,  Man Mui ,  Hao Nguyen ,  Seungpil Lee ,  Deepak Chandra Sekar ,  Tapan Samaddar

IPC分类号： G11C16/24 ,  G11C7/12 ,  G11C16/26

CPC分类号： G11C16/0483 ,  G11C7/12 ,  G11C11/5642 ,  G11C16/24 ,  G11C16/26 ,  G11C2211/5634

摘要： An array of non-volatile storage elements includes a first group of non-volatile storage elements connected to a selected word line, a second group of non-volatile storage elements connected to the selected word line, a first group of bit lines in communication with the first group of non-volatile storage elements, a second group of bit lines in communication with the second group of non-volatile storage elements, a first set of sense modules located at a first location and connected to the first group of bit lines, and a second set of sense modules located at a second location and connected to the second group of bit lines. The first set of sense modules applies a first bit line voltage based on the bit line distance between the first set of sense modules and the first group of non-volatile storage elements. The second set of sense modules applies a second bit line voltage based on the bit line distance between the second set of sense modules and the second group of non-volatile storage elements.

摘要翻译： 非易失性存储元件的阵列包括连接到所选字线的第一组非易失性存储元件，连接到所选择的字线的第二组非易失性存储元件，与所选字线连接的第一组位线 第一组非易失性存储元件，与第二组非易失性存储元件通信的第二组位线，位于第一位置并连接到第一组位线的第一组感测模块， 以及位于第二位置并连接到第二组位线的第二组感测模块。 第一组感测模块基于第一组感测模块和第一组非易失性存储元件之间的位线距离来施加第一位线电压。 第二组感测模块基于第二组感测模块和第二组非易失性存储元件之间的位线距离来施加第二位线电压。

公开(公告)号：US20080068067A1

公开(公告)日：2008-03-20

申请号：US11523875

申请日：2006-09-19

申请人： Prashanti Govindu ,  Feng Pan ,  Man Mui ,  Gyuwan Kwon ,  Trung Pham ,  Chi-Ming Wang

发明人： Prashanti Govindu ,  Feng Pan ,  Man Mui ,  Gyuwan Kwon ,  Trung Pham ,  Chi-Ming Wang

IPC分类号： G05F1/10

CPC分类号： G11C16/30 ,  G11C5/145

摘要： According to different embodiments of the present invention, various methods, devices and systems are described for managing power in charge pumps in a non-volatile memory system having a high voltage charge pump and associated regulator. A method includes the following operations, receiving an operation command corresponding to an operation, pumping up a charge pump output voltage to a desired output voltage, turning off the regulator and the charge pump when the output voltage is approximately the desired output voltage compensating for charge sharing by turning on the charge pump and setting a pump clock rate to a slow clock rate in order to avoid overshooting the desired output voltage by the charge pump while the operation is being carried out, and compensating for junction leakage by turning on the regulator and the charge pump until the charge pump output voltage is the desired output voltage.

摘要翻译： 根据本发明的不同实施例，描述了用于在具有高电压电荷泵和相关联的调节器的非易失性存储器系统中管理电荷泵中的功率的各种方法，装置和系统。 一种方法包括以下操作：当输出电压近似为补偿电荷的期望输出电压时，接收与一个操作对应的操作命令，将电荷泵输出电压泵送到期望的输出电压，关闭调节器和电荷泵 通过打开电荷泵并将泵时钟速率设置为慢时钟速率来共享，以便在执行操作时避免由电荷泵过冲所需的输出电压，以及通过打开调节器来补偿结漏电 电荷泵直到电荷泵输出电压为期望的输出电压。

公开(公告)号：US08081514B2

公开(公告)日：2011-12-20

申请号：US12547449

申请日：2009-08-25

申请人： Man Mui ,  Yingda Dong ,  Binh Lee ,  Deepanshu Dutta

发明人： Man Mui ,  Yingda Dong ,  Binh Lee ,  Deepanshu Dutta

IPC分类号： G11C16/04 ,  G11C16/06

CPC分类号： G11C11/5628 ,  G11C16/0483 ,  G11C16/10 ,  G11C16/3418 ,  G11C16/3427

摘要： Partial speed and full speed programming are achieved for a non-volatile memory system. During a program operation, in a first time period, bit lines of storage elements to be inhibited are pre-charged, while bit line of storage elements to be programmed at a partial speed and bit lines of storage elements to be programmed at a full speed are fixed. In a second time period, the bit lines of storage elements to be programmed at the partial speed are driven higher, while the bit lines of storage elements to be inhibited are floated and the bit line of storage elements to be programmed remain fixed. In a third time period, the bit lines of storage elements to be inhibited are driven higher while the bit lines of the storage elements to be programmed at the partial speed or the full speed are floated so that they couple higher.

摘要翻译： 非易失性存储器系统实现了部分速度和全速编程。 在编程操作期间，在第一时间段中，要禁止的存储元件的位线被预充电，而要以部分速度编程的存储元件的位线和要全速编程的存储元件的位线 是固定的 在第二时间段中，以部分速度编程的存储元件的位线被驱动得较高，而待禁止的存储元件的位线被浮置，并且待编程的存储元件的位线保持固定。 在第三时间段中，待被禁止的存储元件的位线被驱动得较高，而以部分速度或全速编程的存储元件的位线被浮动，使得它们耦合得更高。

公开(公告)号：US07974133B2

公开(公告)日：2011-07-05

申请号：US12349417

申请日：2009-01-06

申请人： Mohan Vamsi Dunga ,  Man Mui ,  Masaaki Higashitani

发明人： Mohan Vamsi Dunga ,  Man Mui ,  Masaaki Higashitani

IPC分类号： G11C11/34

CPC分类号： G11C11/5642 ,  G11C16/26

摘要： A sense amplifier is disclosed. One embodiment is a sensing circuit that includes a sensing device and a sense transistor coupled to the sensing device. A first switch that is coupled to the sense transistor and to the sensing device causes the sensing device to be charged to a first voltage that is a function of the threshold voltage of the sense transistor. One or more second switches that are coupled to the sensing device and to a target element. The second switches couple the sensing device to the target element to modify the first voltage on the sensing device and decouple the target element from the sensing device during a sense phase in which the modified first voltage is applied to the sense transistor. A condition of the target element is determined based on whether or not the sense transistor turns on in response to applying the modified first voltage to the sense transistor.

摘要翻译： 公开了一种读出放大器。 一个实施例是感测电路，其包括耦合到感测装置的感测装置和感测晶体管。 耦合到感测晶体管和感测装置的第一开关使得感测装置被充电到作为感测晶体管的阈值电压的函数的第一电压。 耦合到感测装置和目标元件的一个或多个第二开关。 第二开关将感测装置耦合到目标元件以修改感测装置上的第一电压，并且在将修改的第一电压施加到感测晶体管的感测阶段期间将目标元件与感测装置分离。 目标元件的条件基于响应于将修改的第一电压施加到感测晶体管是否导通而确定。

公开(公告)号：US20110116320A1

公开(公告)日：2011-05-19

申请号：US12617860

申请日：2009-11-13

申请人： Fanglin Zhang ,  Jong Park ,  Man Mui ,  Alexander Chu ,  Seungpil Lee

发明人： Fanglin Zhang ,  Jong Park ,  Man Mui ,  Alexander Chu ,  Seungpil Lee

IPC分类号： G11C16/06

CPC分类号： G11C16/26 ,  G11C11/5642

摘要： In a non-volatile memory system, a voltage generator provides a voltage to a gate of a voltage-setting transistor which is used in a sense circuit to set an initial voltage at a sense node. At the end of a sense period, a final voltage of the sense node is compared to a trip point, which is the threshold voltage of a voltage-sensing transistor. To account for temperature variations and manufacturing process variations, the voltage generator includes a transistor which is matched to the voltage-setting transistor, and a transistor which is matched to the voltage-sensing transistor. As a result, a voltage swing between the initial voltage and the trip point is constant, even as the initial voltage and trip point vary. In a particular implementation, the voltage generator uses a cascode current mirror circuit, and receives a reference current from a band gap voltage circuit.

摘要翻译： 在非易失性存储器系统中，电压发生器向用于感测电路的电压设置晶体管的栅极提供电压，以在感测节点处设置初始电压。 在感测周期结束时，将感测节点的最终电压与作为电压感测晶体管的阈值电压的跳变点进行比较。 为了解决温度变化和制造工艺变化，电压发生器包括与电压设定晶体管相匹配的晶体管和与电压感测晶体管匹配的晶体管。 结果，即使初始电压和跳变点变化，初始电压和跳闸点之间的电压摆动也是恒定的。 在特定实施方案中，电压发生器使用共源共栅电流镜电路，并从带隙电压电路接收参考电流。

公开(公告)号：US07551477B2

公开(公告)日：2009-06-23

申请号：US11861571

申请日：2007-09-26

申请人： Nima Mokhlesi ,  Dengtao Zhao ,  Man Mui ,  Hao Nguyen ,  Seungpil Lee ,  Deepak Chandra Sekar ,  Tapan Samaddar

发明人： Nima Mokhlesi ,  Dengtao Zhao ,  Man Mui ,  Hao Nguyen ,  Seungpil Lee ,  Deepak Chandra Sekar ,  Tapan Samaddar

IPC分类号： G11C11/34

CPC分类号： G11C16/0483 ,  G11C7/12 ,  G11C11/5642 ,  G11C16/24 ,  G11C16/26 ,  G11C2211/5634

摘要： An array of non-volatile storage elements includes a first group of non-volatile storage elements connected to a selected word line, a second group of non-volatile storage elements connected to the selected word line, a first group of bit lines in communication with the first group of non-volatile storage elements, a second group of bit lines in communication with the second group of non-volatile storage elements, a first set of sense modules located at a first location and connected to the first group of bit lines, and a second set of sense modules located at a second location and connected to the second group of bit lines. The first set of sense modules applies a first bit line voltage based on the bit line distance between the first set of sense modules and the first group of non-volatile storage elements. The second set of sense modules applies a second bit line voltage based on the bit line distance between the second set of sense modules and the second group of non-volatile storage elements.

摘要翻译： 非易失性存储元件的阵列包括连接到所选字线的第一组非易失性存储元件，连接到所选择的字线的第二组非易失性存储元件，与所选字线连接的第一组位线 第一组非易失性存储元件，与第二组非易失性存储元件通信的第二组位线，位于第一位置并连接到第一组位线的第一组感测模块， 以及位于第二位置并连接到第二组位线的第二组感测模块。 第一组感测模块基于第一组感测模块和第一组非易失性存储元件之间的位线距离来施加第一位线电压。 第二组感测模块基于第二组感测模块和第二组非易失性存储元件之间的位线距离来施加第二位线电压。

公开(公告)号：US07368979B2

公开(公告)日：2008-05-06

申请号：US11523875

申请日：2006-09-19

申请人： Prashanti Govindu ,  Feng Pan ,  Man Mui ,  Gyuwan Kwon ,  Trung Pham ,  Chi-Ming Wang

发明人： Prashanti Govindu ,  Feng Pan ,  Man Mui ,  Gyuwan Kwon ,  Trung Pham ,  Chi-Ming Wang

IPC分类号： G05F1/10

CPC分类号： G11C16/30 ,  G11C5/145

摘要： According to different embodiments of the present invention, various methods, devices and systems are described for managing power in charge pumps in a non-volatile memory system having a high voltage charge pump and associated regulator. A method includes the following operations, receiving an operation command corresponding to an operation, pumping up a charge pump output voltage to a desired output voltage, turning off the regulator and the charge pump when the output voltage is approximately the desired output voltage compensating for charge sharing by turning on the charge pump and setting a pump clock rate to a slow clock rate in order to avoid overshooting the desired output voltage by the charge pump while the operation is being carried out, and compensating for junction leakage by turning on the regulator and the charge pump until the charge pump output voltage is the desired output voltage.

摘要翻译： 根据本发明的不同实施例，描述了用于在具有高电压电荷泵和相关联的调节器的非易失性存储器系统中管理电荷泵中的功率的各种方法，装置和系统。 一种方法包括以下操作：当输出电压近似为补偿电荷的期望输出电压时，接收与一个操作对应的操作命令，将电荷泵输出电压泵送到期望的输出电压，关闭调节器和电荷泵 通过打开电荷泵并将泵时钟速率设置为慢时钟速率来共享，以便在执行操作时避免由电荷泵过冲所需的输出电压，以及通过打开调节器来补偿结漏电 电荷泵直到电荷泵输出电压为期望的输出电压。

公开(公告)号：US07974134B2

公开(公告)日：2011-07-05

申请号：US12617860

申请日：2009-11-13

申请人： Fanglin Zhang ,  Jong Park ,  Man Mui ,  Alexander Chu ,  Seungpil Lee

发明人： Fanglin Zhang ,  Jong Park ,  Man Mui ,  Alexander Chu ,  Seungpil Lee

IPC分类号： G11C16/06

CPC分类号： G11C16/26 ,  G11C11/5642

摘要： In a non-volatile memory system, a voltage generator provides a voltage to a gate of a voltage-setting transistor which is used in a sense circuit to set an initial voltage at a sense node. At the end of a sense period, a final voltage of the sense node is compared to a trip point, which is the threshold voltage of a voltage-sensing transistor. To account for temperature variations and manufacturing process variations, the voltage generator includes a transistor which is matched to the voltage-setting transistor, and a transistor which is matched to the voltage-sensing transistor. As a result, a voltage swing between the initial voltage and the trip point is constant, even as the initial voltage and trip point vary. In a particular implementation, the voltage generator uses a cascode current mirror circuit, and receives a reference current from a band gap voltage circuit.

摘要翻译： 在非易失性存储器系统中，电压发生器向用于感测电路的电压设置晶体管的栅极提供电压，以在感测节点处设置初始电压。 在感测周期结束时，将感测节点的最终电压与作为电压感测晶体管的阈值电压的跳变点进行比较。 为了解决温度变化和制造工艺变化，电压发生器包括与电压设定晶体管相匹配的晶体管和与电压感测晶体管匹配的晶体管。 结果，即使初始电压和跳变点变化，初始电压和跳闸点之间的电压摆动也是恒定的。 在特定实施方案中，电压发生器使用共源共栅电流镜电路，并从带隙电压电路接收参考电流。

公开(公告)号：US20110051517A1

公开(公告)日：2011-03-03

申请号：US12547449

申请日：2009-08-25

申请人： Man Mui ,  Yingda Dong ,  Binh Le ,  Deepanshu Dutta

发明人： Man Mui ,  Yingda Dong ,  Binh Le ,  Deepanshu Dutta

IPC分类号： G11C16/04 ,  G11C16/06

CPC分类号： G11C11/5628 ,  G11C16/0483 ,  G11C16/10 ,  G11C16/3418 ,  G11C16/3427

摘要： Partial speed and full speed programming are achieved for a non-volatile memory system. During a program operation, in a first time period, bit lines of storage elements to be inhibited are pre-charged, while bit line of storage elements to be programmed at a partial speed and bit lines of storage elements to be programmed at a full speed are fixed. In a second time period, the bit lines of storage elements to be programmed at the partial speed are driven higher, while the bit lines of storage elements to be inhibited are floated and the bit line of storage elements to be programmed remain fixed. In a third time period, the bit lines of storage elements to be inhibited are driven higher while the bit lines of the storage elements to be programmed at the partial speed or the full speed are floated so that they couple higher.

摘要翻译： 非易失性存储器系统实现了部分速度和全速编程。 在编程操作期间，在第一时间段中，要禁止的存储元件的位线被预充电，而要以部分速度编程的存储元件的位线和要全速编程的存储元件的位线 是固定的 在第二时间段中，以部分速度编程的存储元件的位线被驱动得较高，而待禁止的存储元件的位线被浮置，并且待编程的存储元件的位线保持固定。 在第三时间段中，待被禁止的存储元件的位线被驱动得较高，而以部分速度或全速编程的存储元件的位线被浮动，使得它们耦合得更高。