公开(公告)号：US20090080265A1

公开(公告)日：2009-03-26

申请号：US11861571

申请日：2007-09-26

申请人： Nima Mokhlesi ,  Dengtao Zhao ,  Man Mui ,  Hao Nguyen ,  Seungpil Lee ,  Deepak Chandra Sekar ,  Tapan Samaddar

发明人： Nima Mokhlesi ,  Dengtao Zhao ,  Man Mui ,  Hao Nguyen ,  Seungpil Lee ,  Deepak Chandra Sekar ,  Tapan Samaddar

IPC分类号： G11C16/24 ,  G11C7/12 ,  G11C16/26

CPC分类号： G11C16/0483 ,  G11C7/12 ,  G11C11/5642 ,  G11C16/24 ,  G11C16/26 ,  G11C2211/5634

摘要： An array of non-volatile storage elements includes a first group of non-volatile storage elements connected to a selected word line, a second group of non-volatile storage elements connected to the selected word line, a first group of bit lines in communication with the first group of non-volatile storage elements, a second group of bit lines in communication with the second group of non-volatile storage elements, a first set of sense modules located at a first location and connected to the first group of bit lines, and a second set of sense modules located at a second location and connected to the second group of bit lines. The first set of sense modules applies a first bit line voltage based on the bit line distance between the first set of sense modules and the first group of non-volatile storage elements. The second set of sense modules applies a second bit line voltage based on the bit line distance between the second set of sense modules and the second group of non-volatile storage elements.

摘要翻译： 非易失性存储元件的阵列包括连接到所选字线的第一组非易失性存储元件，连接到所选择的字线的第二组非易失性存储元件，与所选字线连接的第一组位线 第一组非易失性存储元件，与第二组非易失性存储元件通信的第二组位线，位于第一位置并连接到第一组位线的第一组感测模块， 以及位于第二位置并连接到第二组位线的第二组感测模块。 第一组感测模块基于第一组感测模块和第一组非易失性存储元件之间的位线距离来施加第一位线电压。 第二组感测模块基于第二组感测模块和第二组非易失性存储元件之间的位线距离来施加第二位线电压。

公开(公告)号：US07551477B2

公开(公告)日：2009-06-23

申请号：US11861571

申请日：2007-09-26

申请人： Nima Mokhlesi ,  Dengtao Zhao ,  Man Mui ,  Hao Nguyen ,  Seungpil Lee ,  Deepak Chandra Sekar ,  Tapan Samaddar

发明人： Nima Mokhlesi ,  Dengtao Zhao ,  Man Mui ,  Hao Nguyen ,  Seungpil Lee ,  Deepak Chandra Sekar ,  Tapan Samaddar

IPC分类号： G11C11/34

CPC分类号： G11C16/0483 ,  G11C7/12 ,  G11C11/5642 ,  G11C16/24 ,  G11C16/26 ,  G11C2211/5634

摘要： An array of non-volatile storage elements includes a first group of non-volatile storage elements connected to a selected word line, a second group of non-volatile storage elements connected to the selected word line, a first group of bit lines in communication with the first group of non-volatile storage elements, a second group of bit lines in communication with the second group of non-volatile storage elements, a first set of sense modules located at a first location and connected to the first group of bit lines, and a second set of sense modules located at a second location and connected to the second group of bit lines. The first set of sense modules applies a first bit line voltage based on the bit line distance between the first set of sense modules and the first group of non-volatile storage elements. The second set of sense modules applies a second bit line voltage based on the bit line distance between the second set of sense modules and the second group of non-volatile storage elements.

摘要翻译： 非易失性存储元件的阵列包括连接到所选字线的第一组非易失性存储元件，连接到所选择的字线的第二组非易失性存储元件，与所选字线连接的第一组位线 第一组非易失性存储元件，与第二组非易失性存储元件通信的第二组位线，位于第一位置并连接到第一组位线的第一组感测模块， 以及位于第二位置并连接到第二组位线的第二组感测模块。 第一组感测模块基于第一组感测模块和第一组非易失性存储元件之间的位线距离来施加第一位线电压。 第二组感测模块基于第二组感测模块和第二组非易失性存储元件之间的位线距离来施加第二位线电压。

公开(公告)号：US08472255B2

公开(公告)日：2013-06-25

申请号：US13605714

申请日：2012-09-06

申请人： Nima Mokhlesi ,  Dengtao Zhao ,  Henry Chin ,  Tapan Samaddar

发明人： Nima Mokhlesi ,  Dengtao Zhao ,  Henry Chin ,  Tapan Samaddar

IPC分类号： G11C11/34

CPC分类号： G11C16/12 ,  G11C11/5628 ,  G11C16/04 ,  G11C16/0483 ,  G11C16/10 ,  G11C29/00 ,  G11C29/02 ,  G11C29/021 ,  G11C29/028

摘要： To program a set of non-volatile storage elements, a set of programming pulses are applied to the control gates (or other terminals) of the non-volatile storage elements. The programming pulses have pulse widths that vary as a function of simulated pulse magnitude data. The programming pulses can also have pulse magnitudes that vary based on measurements taken while testing the set of non-volatile storage elements. In one embodiment, the pulse widths are determined after simulation performed prior to fabrication of the non-volatile storage elements. In another embodiment, the pulse magnitudes are calculated after fabrication of the non-volatile storage elements.

摘要翻译： 为了对一组非易失性存储元件进行编程，将一组编程脉冲施加到非易失性存储元件的控制门（或其它终端）。 编程脉冲具有根据模拟脉冲幅度数据变化的脉冲宽度。 编程脉冲还可以具有基于在测试该组非易失性存储元件时所采取的测量而变化的脉冲幅度。 在一个实施例中，在制造非易失性存储元件之前进行仿真之后确定脉冲宽度。 在另一个实施例中，在制造非易失性存储元件之后计算脉冲幅度。

公开(公告)号：US20110235428A1

公开(公告)日：2011-09-29

申请号：US13151938

申请日：2011-06-02

申请人： Nima Mokhlesi ,  Dengtao Zhao ,  Henry Chin ,  Tapan Samaddar

发明人： Nima Mokhlesi ,  Dengtao Zhao ,  Henry Chin ,  Tapan Samaddar

IPC分类号： G11C16/10

CPC分类号： G11C16/12 ,  G11C11/5628 ,  G11C16/04 ,  G11C16/0483 ,  G11C16/10 ,  G11C29/00 ,  G11C29/02 ,  G11C29/021 ,  G11C29/028

摘要： To program a set of non-volatile storage elements, a set of programming pulses are applied to the control gates (or other terminals) of the non-volatile storage elements. The programming pulses have pulse widths that vary as a function of simulated pulse magnitude data. The programming pulses can also have pulse magnitudes that vary based on measurements taken while testing the set of non-volatile storage elements. In one embodiment, the pulse widths are determined after simulation performed prior to fabrication of the non-volatile storage elements. In another embodiment, the pulse magnitudes are calculated after fabrication of the non-volatile storage elements.

摘要翻译： 为了对一组非易失性存储元件进行编程，将一组编程脉冲施加到非易失性存储元件的控制门（或其它终端）。 编程脉冲具有根据模拟脉冲幅度数据变化的脉冲宽度。 编程脉冲还可以具有基于在测试该组非易失性存储元件时所采取的测量而变化的脉冲幅度。 在一个实施例中，在制造非易失性存储元件之前进行仿真之后确定脉冲宽度。 在另一个实施例中，在制造非易失性存储元件之后计算脉冲幅度。

公开(公告)号：US20090086544A1

公开(公告)日：2009-04-02

申请号：US11862485

申请日：2007-09-27

申请人： Nima Mokhlesi ,  Dengtao Zhao ,  Henry Chin ,  Tapan Samaddar

发明人： Nima Mokhlesi ,  Dengtao Zhao ,  Henry Chin ,  Tapan Samaddar

IPC分类号： G11C16/04

CPC分类号： G11C16/12 ,  G11C11/5628 ,  G11C16/04 ,  G11C16/0483 ,  G11C16/10 ,  G11C29/00 ,  G11C29/02 ,  G11C29/021 ,  G11C29/028

摘要： To program a set of non-volatile storage elements, a set of programming pulses are applied to the control gates (or other terminals) of the non-volatile storage elements. The programming pulses have pulse widths that vary as a function of simulated pulse magnitude data. The programming pulses can also have pulse magnitudes that vary based on measurements taken while testing the set of non-volatile storage elements. In one embodiment, the pulse widths are determined after simulation performed prior to fabrication of the non-volatile storage elements. In another embodiment, the pulse magnitudes are calculated after fabrication of the non-volatile storage elements.

摘要翻译： 为了对一组非易失性存储元件进行编程，将一组编程脉冲施加到非易失性存储元件的控制门（或其它终端）。 编程脉冲具有根据模拟脉冲幅度数据变化的脉冲宽度。 编程脉冲还可以具有基于在测试该组非易失性存储元件时所采取的测量而变化的脉冲幅度。 在一个实施例中，在制造非易失性存储元件之前进行仿真之后确定脉冲宽度。 在另一个实施例中，在制造非易失性存储元件之后计算脉冲幅度。

公开(公告)号：US20120327716A1

公开(公告)日：2012-12-27

申请号：US13605714

申请日：2012-09-06

申请人： Nima Mokhlesi ,  Dengtao Zhao ,  Henry Chin ,  Tapan Samaddar

发明人： Nima Mokhlesi ,  Dengtao Zhao ,  Henry Chin ,  Tapan Samaddar

IPC分类号： G11C16/10

CPC分类号： G11C16/12 ,  G11C11/5628 ,  G11C16/04 ,  G11C16/0483 ,  G11C16/10 ,  G11C29/00 ,  G11C29/02 ,  G11C29/021 ,  G11C29/028

摘要： To program a set of non-volatile storage elements, a set of programming pulses are applied to the control gates (or other terminals) of the non-volatile storage elements. The programming pulses have pulse widths that vary as a function of simulated pulse magnitude data. The programming pulses can also have pulse magnitudes that vary based on measurements taken while testing the set of non-volatile storage elements. In one embodiment, the pulse widths are determined after simulation performed prior to fabrication of the non-volatile storage elements. In another embodiment, the pulse magnitudes are calculated after fabrication of the non-volatile storage elements.

摘要翻译： 为了对一组非易失性存储元件进行编程，将一组编程脉冲施加到非易失性存储元件的控制门（或其它终端）。 编程脉冲具有根据模拟脉冲幅度数据变化的脉冲宽度。 编程脉冲还可以具有基于在测试该组非易失性存储元件时所采取的测量而变化的脉冲幅度。 在一个实施例中，在制造非易失性存储元件之前进行仿真之后确定脉冲宽度。 在另一个实施例中，在制造非易失性存储元件之后计算脉冲幅度。

公开(公告)号：US08284609B2

公开(公告)日：2012-10-09

申请号：US13151938

申请日：2011-06-02

申请人： Nima Mokhlesi ,  Dengtao Zhao ,  Henry Chin ,  Tapan Samaddar

发明人： Nima Mokhlesi ,  Dengtao Zhao ,  Henry Chin ,  Tapan Samaddar

IPC分类号： G11C11/34 ,  G11C16/04

CPC分类号： G11C16/12 ,  G11C11/5628 ,  G11C16/04 ,  G11C16/0483 ,  G11C16/10 ,  G11C29/00 ,  G11C29/02 ,  G11C29/021 ,  G11C29/028

摘要： To program a set of non-volatile storage elements, a set of programming pulses are applied to the control gates (or other terminals) of the non-volatile storage elements. The programming pulses have pulse widths that vary as a function of simulated pulse magnitude data. The programming pulses can also have pulse magnitudes that vary based on measurements taken while testing the set of non-volatile storage elements. In one embodiment, the pulse widths are determined after simulation performed prior to fabrication of the non-volatile storage elements. In another embodiment, the pulse magnitudes are calculated after fabrication of the non-volatile storage elements.

摘要翻译： 为了对一组非易失性存储元件进行编程，将一组编程脉冲施加到非易失性存储元件的控制门（或其它终端）。 编程脉冲具有根据模拟脉冲幅度数据变化的脉冲宽度。 编程脉冲还可以具有基于在测试该组非易失性存储元件时所采取的测量而变化的脉冲幅度。 在一个实施例中，在制造非易失性存储元件之前进行仿真之后确定脉冲宽度。 在另一个实施例中，在制造非易失性存储元件之后计算脉冲幅度。

公开(公告)号：US07978520B2

公开(公告)日：2011-07-12

申请号：US11862485

申请日：2007-09-27

申请人： Nima Mokhlesi ,  Dengtao Zhao ,  Henry Chin ,  Tapan Samaddar

发明人： Nima Mokhlesi ,  Dengtao Zhao ,  Henry Chin ,  Tapan Samaddar

IPC分类号： G11C16/04

CPC分类号： G11C16/12 ,  G11C11/5628 ,  G11C16/04 ,  G11C16/0483 ,  G11C16/10 ,  G11C29/00 ,  G11C29/02 ,  G11C29/021 ,  G11C29/028

摘要： To program a set of non-volatile storage elements, a set of programming pulses are applied to the control gates (or other terminals) of the non-volatile storage elements. The programming pulses have pulse widths that vary as a function of simulated pulse magnitude data. The programming pulses can also have pulse magnitudes that vary based on measurements taken while testing the set of non-volatile storage elements. In one embodiment, the pulse widths are determined after simulation performed prior to fabrication of the non-volatile storage elements. In another embodiment, the pulse magnitudes are calculated after fabrication of the non-volatile storage elements.

摘要翻译： 为了对一组非易失性存储元件进行编程，将一组编程脉冲施加到非易失性存储元件的控制门（或其它终端）。 编程脉冲具有根据模拟脉冲幅度数据变化的脉冲宽度。 编程脉冲还可以具有基于在测试该组非易失性存储元件时所采取的测量而变化的脉冲幅度。 在一个实施例中，在制造非易失性存储元件之前进行仿真之后确定脉冲宽度。 在另一个实施例中，在制造非易失性存储元件之后计算脉冲幅度。

公开(公告)号：US07463528B2

公开(公告)日：2008-12-09

申请号：US11958534

申请日：2007-12-18

申请人： Nima Mokhlesi ,  Dengtao Zhao

发明人： Nima Mokhlesi ,  Dengtao Zhao

IPC分类号： G11C11/34 ,  G11C16/06

CPC分类号： G11C7/04 ,  G11C11/5628 ,  G11C11/5642 ,  G11C16/0483 ,  G11C16/12 ,  G11C16/26 ,  G11C16/3454 ,  G11C16/3459 ,  G11C2211/5621

摘要： Reading and verify operations are performed on non-volatile storage elements using temperature-compensated read voltages for unselected word lines, and/or for select gates such as drain or source side select gates of a NAND string. In one approach, while a read or verify voltage is applied to a selected word line, temperature-compensated read voltages are applied to unselected word lines and select gates. Word lines which directly neighbor the selected word line can receive a voltage which is not temperature compensated, or which is temperature-compensated to a reduced degree. The read or verify voltage applied to the selected word line can also be temperature-compensated. The temperature compensation may also account for word line position.

摘要翻译： 使用非选择字线的温度补偿读取电压和/或用于NAND串的漏极或源极选择栅极的选择栅极对非易失性存储元件执行读取和验证操作。 在一种方法中，当读取或验证电压被施加到所选择的字线时，温度补偿的读取电压被施加到未选择的字线并选择栅极。 直接与所选字线相邻的字线可以接收不被温度补偿的电压，或者被降低程度的温度补偿。 施加到所选字线的读取或验证电压也可以进行温度补偿。 温度补偿也可以说明字线位置。

公开(公告)号：US20080273388A1

公开(公告)日：2008-11-06

申请号：US11688874

申请日：2007-03-21

申请人： Henry Chin ,  Nima Mokhlesi ,  Dengtao Zhao

发明人： Henry Chin ,  Nima Mokhlesi ,  Dengtao Zhao

IPC分类号： G11C11/34

CPC分类号： G11C16/0483 ,  G11C11/5628 ,  G11C16/10 ,  G11C16/3454

摘要： In some non-volatile storage systems, a block of data memory cells is manufactured with a dummy word line at the bottom of the block, at the top of the block, and/or at other locations. By selectively programming memory cells on the dummy word line(s), the resistances associated with the data memory cells can be changed to account for different programmed data patterns.

摘要翻译： 在一些非易失性存储系统中，在块的底部，块的顶部和/或其他位置处制造具有伪字线的数据存储单元块。 通过选择性地编程虚拟字线上的存储器单元，可以改变与数据存储单元相关联的电阻以考虑不同的编程数据模式。