Abstract:
In a serial communication system having a device including a receiver detection module, this specification is directed to systems and methods for selectively reducing the power consumed by the receiver detection module, preferably when the device is operating in a low power mode. In some embodiments, a signal detection module is configured to receive a control signal from the transmitter of a device at the other end of the communications link to control the operation of the receiver detection module. The control signal may be in-band or may be transmitted on a sideband of the serial link.
Abstract:
In a serial communication system having a device including a receiver detection module, this specification is directed to systems and methods for selectively reducing the power consumed by the receiver detection module, preferably when the device is operating in a low power mode. In some embodiments, a signal detection module is configured to receive a control signal from the transmitter of a device at the other end of the communications link to control the operation of the receiver detection module. The control signal may be in-band or may be transmitted on a sideband of the serial link.
Abstract:
Embodiments of the present invention provide a high throughput, low pin count, low power, and small area solution for the interface between a host device and a wireless communication circuit. In one embodiment of the invention, a system for wireless communication using a host-slave interface is disclosed. The system is comprised of a host device having a slave interface, and a wireless communication circuit having a master interface coupled to the host device's slave interface. The wireless communication circuit transfers data between a wireless network and the host device. Using such a system, a wireless communication system with a host-slave interface is produced.
Abstract:
A method of and system for generating tests and using the tests to identify VLSI simulation and circuit operation faults and errors and validate performance uses a genetic algorithm. Each generation of tests is further processed to eliminate redundant tests and make room for the insertion of new genetic material into the population in the form of random test vectors. The resulting family of tests generated using a simulation of the VLSI can then be ported to the circuit once prototyped in silicon and adapted to the new environment using, once again, the genetic algorithm to suitably evolve the test population.