公开(公告)号：US08995207B2

公开(公告)日：2015-03-31

申请号：US13208450

申请日：2011-08-12

申请人： Christopher Edward Koob ,  Jen Tsung Lin ,  Manojkumar Pyla ,  Martin Saint-Laurent

发明人： Christopher Edward Koob ,  Jen Tsung Lin ,  Manojkumar Pyla ,  Martin Saint-Laurent

IPC分类号： G11C7/00 ,  G06F5/06 ,  G11C5/14

CPC分类号： G06F5/06 ,  G06F5/10 ,  G06F5/14 ,  G06F2205/102 ,  G11C5/145

摘要： According to an embodiment, an apparatus includes a data storage device. Data to be stored in the data storage device is level shifted from a first voltage domain to a second voltage domain prior to being stored within the data storage device. The data storage device is powered by the second voltage domain. The apparatus further includes a circuit that is powered by the second voltage domain and that is responsive to data output by the data storage device.

摘要翻译： 根据实施例，一种装置包括数据存储装置。 要存储在数据存储设备中的数据在被存储在数据存储设备中之前从第一电压域电平移位到第二电压域。 数据存储设备由第二电压域供电。 该装置还包括由第二电压域供电并且响应于数据存储装置输出的数据的电路。

公开(公告)号：US08370806B2

公开(公告)日：2013-02-05

申请号：US11560217

申请日：2006-11-15

申请人： Lucian Codrescu ,  William C. Anderson ,  Suresh Venkumahanti ,  Louis Achille Giannini ,  Manojkumar Pyla ,  Xufeng Chen

发明人： Lucian Codrescu ,  William C. Anderson ,  Suresh Venkumahanti ,  Louis Achille Giannini ,  Manojkumar Pyla ,  Xufeng Chen

IPC分类号： G06F9/44

CPC分类号： G06F9/3005 ,  G06F9/3009 ,  G06F9/3851 ,  G06F11/362

摘要： A method and system provide processing instructions in a multi-threaded process including the use of breakpoint instructions for generating debugging event(s). A debugging event is generated in response to the execution of breakpoint instructions and executes debugging instructions in response to the debugging event. The debugging instructions debug processing instructions in the multi-threaded processor by transitioning at least one or more threads into a debugging mode. A debugging return is generated for reporting the executing debugging instructions in the subset of the threads of the multi-threaded processor.

摘要翻译： 一种方法和系统在多线程过程中提供处理指令，包括使用断点指令来产生调试事件。 响应于断点指令的执行而生成调试事件，并响应调试事件执行调试指令。 调试指令通过将至少一个或多个线程转换为调试模式来调试多线程处理器中的处理指令。 生成调试返回以报告多线程处理器的线程子集中执行的调试指令。

公开(公告)号：US07657791B2

公开(公告)日：2010-02-02

申请号：US11560323

申请日：2006-11-15

申请人： Lucian Codrescu ,  William C. Anderson ,  Suresh Venkumahanti ,  Louis Achille Giannini ,  Manojkumar Pyla ,  Xufeng Chen

发明人： Lucian Codrescu ,  William C. Anderson ,  Suresh Venkumahanti ,  Louis Achille Giannini ,  Manojkumar Pyla ,  Xufeng Chen

IPC分类号： G06F11/00

CPC分类号： G06F1/3203 ,  G06F11/362 ,  G06F11/3656

摘要： Techniques for the design and use of a digital signal processor, including (but not limited to) for processing transmissions in a communications (e.g., CDMA) system. A method and system control transferring data between debugging registers and digital signal processor processes in association with a power transition sequence of the digital signal processor. In a digital signal processor, debugging registers associate with the core processor process and the debugging process. Control bits control transferring data among the debugging registers, the core processor process and the debugging process. The control bit prevents transferring data among the debugging registers, the core processor process and the debugging process in the event of a power transition sequence. Control bits also prevent a power transition sequence of the digital signal processor in the event of transferring data among the debugging registers and the core processor process or the debugging process.

摘要翻译： 用于设计和使用数字信号处理器的技术，包括（但不限于）用于处理通信（例如，CDMA）系统中的传输。 一种与数字信号处理器的功率转换序列相关联的在调试寄存器和数字信号处理器处理之间传送数据的方法和系统控制。 在数字信号处理器中，调试寄存器与核心处理器进程和调试过程相关联。 控制位控制在调试寄存器，核心处理器进程和调试过程之间传输数据。 控制位防止在电源转换序列的情况下在调试寄存器，核心处理器进程和调试过程之间传输数据。 在调试寄存器和核心处理器处理或调试过程之间传输数据的情况下，控制位还可以防止数字信号处理器的电源转换序列。

公开(公告)号：US20080115145A1

公开(公告)日：2008-05-15

申请号：US11560323

申请日：2006-11-15

申请人： Lucian Codrescu ,  William C. Anderson ,  Suresh Venkumahanti ,  Louis Achille Giannini ,  Manojkumar Pyla ,  Xufeng Chen

发明人： Lucian Codrescu ,  William C. Anderson ,  Suresh Venkumahanti ,  Louis Achille Giannini ,  Manojkumar Pyla ,  Xufeng Chen

IPC分类号： G06F3/00

CPC分类号： G06F1/3203 ,  G06F11/362 ,  G06F11/3656

摘要： Techniques for the design and use of a digital signal processor, including (but not limited to) fox processing transmissions in a communications (e.g., CDMA) system. A method and system control transferring data between debugging registers and digital signal processor processes in association with a power transition sequence of the digital signal processor. In a digital signal processor, debugging registers associate with the core processor process and the debugging process. Control bits control transferring data among the debugging registers, the core processor process and the debugging process. The control bit prevents transferring data among the debugging registers, the core processor process and the debugging process in the event of a power transition sequence. Control bits also prevent a power transition sequence of the digital signal processor in the event of transferring data among the debugging registers and the core processor process or the debugging process.

摘要翻译： 在通信（例如CDMA）系统中设计和使用数字信号处理器的技术，包括（但不限于）狐狸处理传输。 一种与数字信号处理器的功率转换序列相关联的在调试寄存器和数字信号处理器处理之间传送数据的方法和系统控制。 在数字信号处理器中，调试寄存器与核心处理器进程和调试过程相关联。 控制位控制在调试寄存器，核心处理器进程和调试过程之间传输数据。 控制位防止在电源转换序列的情况下在调试寄存器，核心处理器进程和调试过程之间传输数据。 在调试寄存器和核心处理器处理或调试过程之间传送数据的情况下，控制位还可以防止数字信号处理器的电源转换序列。

公开(公告)号：US20080115011A1

公开(公告)日：2008-05-15

申请号：US11560332

申请日：2006-11-15

申请人： Lucian Codrescu ,  William C. Anderson ,  Suresh Venkumahanti ,  Louis Achille Giannini ,  Manojkumar Pyla ,  Xufeng Chen

发明人： Lucian Codrescu ,  William C. Anderson ,  Suresh Venkumahanti ,  Louis Achille Giannini ,  Manojkumar Pyla ,  Xufeng Chen

IPC分类号： G06F11/36 ,  G06F9/44

CPC分类号： G06F11/3656

摘要： Techniques for the design and use of a digital signal processor, including (but not limited to) for processing transmissions in a communications (e.g., CDMA) system. Trusted and untrusted debugging operational control occurs in operating a core processor associated with the digital signal processor. A debugging process within a debugging mechanism associates with the core processor. The core processor process determines the origin of debugging control as trusted debugging control or untrusted debugging control. In the event of trusted debugging control, the core processor process provides to the trusted debugging control a first set of features and privileges. Alternatively, in the event that debugging control is untrusted debugging control, the core processor process provides the untrusted debugging control a second restricted set of features and privileges, all for maintaining security and proper operation of the core processor process.

摘要翻译： 用于设计和使用数字信号处理器的技术，包括（但不限于）用于处理通信（例如，CDMA）系统中的传输。 在操作与数字信号处理器相关联的核心处理器时，发生信任和不信任的调试操作控制。 调试机制中的调试过程与核心处理器相关联。 核心处理器过程将调试控制的起源确定为可信的调试控制或不可信的调试控制。 在受信任的调试控制的情况下，核心处理器进程向受信任的调试控制提供了第一组功能和特权。 或者，如果调试控制是不可信任的调试控制，则核心处理器进程将不可信任的调试控制提供第二受限制的功能和特权集，以保持核心处理器进程的安全性和正常运行。

公开(公告)号：US08380966B2

公开(公告)日：2013-02-19

申请号：US11560344

申请日：2006-11-15

申请人： Lucian Codrescu ,  William C. Anderson ,  Suresh Venkumahanti ,  Louis Achille Giannini ,  Manojkumar Pyla ,  Xufeng Chen

发明人： Lucian Codrescu ,  William C. Anderson ,  Suresh Venkumahanti ,  Louis Achille Giannini ,  Manojkumar Pyla ,  Xufeng Chen

IPC分类号： G06F11/00

CPC分类号： G06F11/362 ,  G06F11/3656

摘要： Techniques for the design and use of a digital signal processor, including (but not limited to) for processing transmissions in a communications (e.g., CDMA) system. Stuffing instructions in a processing pipeline of a multi-threaded digital signal processor provides for operating a core processor process and a debugging process within a debugging mechanism. Writing a stuff instruction into a debugging process registry and a stuff command in a debugging process command register provides for identifying a predetermined thread of the multi-threaded digital signal processor in which to execute the stuff instruction. The instruction stuffing process issues a debugging process control resume command during a predetermined stage of executing on the predetermined thread and directs the core processor to perform the stuff instruction during the debugging process. The core processor may then execute the stuffed instruction in association with the core processor process and the debugging process.

摘要翻译： 用于设计和使用数字信号处理器的技术，包括（但不限于）用于处理通信（例如，CDMA）系统中的传输。 在多线程数字信号处理器的处理流水线中的填充指令提供了在调试机制内操作核心处理器进程和调试过程。 将填充指令写入调试进程注册表，并且调试进程命令寄存器中的填充命令用于标识执行填充指令的多线程数字信号处理器的预定线程。 指令填充处理在预定线程的预定执行阶段发出调试过程控制恢复命令，并指示核心处理器在调试过程中执行填充指令。 核心处理器然后可以与核心处理器进程和调试过程相关联地执行填充指令。

公开(公告)号：US20130039133A1

公开(公告)日：2013-02-14

申请号：US13208450

申请日：2011-08-12

申请人： Christopher Edward Koob ,  Jen Tsung Lin ,  Manojkumar Pyla ,  Martin Saint-Laurent

发明人： Christopher Edward Koob ,  Jen Tsung Lin ,  Manojkumar Pyla ,  Martin Saint-Laurent

IPC分类号： G11C5/14

CPC分类号： G06F5/06 ,  G06F5/10 ,  G06F5/14 ,  G06F2205/102 ,  G11C5/145

摘要： According to an embodiment, an apparatus includes a data storage device. Data to be stored in the data storage device is level shifted from a first voltage domain to a second voltage domain prior to being stored within the data storage device. The data storage device is powered by the second voltage domain. The apparatus further includes a circuit that is powered by the second voltage domain and that is responsive to data output by the data storage device.

摘要翻译： 根据实施例，一种装置包括数据存储装置。 要存储在数据存储设备中的数据在被存储在数据存储设备中之前从第一电压域电平移位到第二电压域。 数据存储设备由第二电压域供电。 该装置还包括由第二电压域供电并且响应于数据存储装置输出的数据的电路。

公开(公告)号：US20080313442A1

公开(公告)日：2008-12-18

申请号：US11762647

申请日：2007-06-13

申请人： Jian Wei ,  Manojkumar Pyla ,  Xufeng Chen

发明人： Jian Wei ,  Manojkumar Pyla ,  Xufeng Chen

IPC分类号： G06F9/30

CPC分类号： G06F11/2236

摘要： Techniques for debugging a programmable integrated circuit are described. Embodiments include steps of initiating instruction-cache-misses in the integrated circuit using a remote computer executing a test program; substituting, during an instruction-cache-miss event, instructions in the application program with test instructions provided by the test program; and debugging the integrated circuit based on analysis of its responses to the test instructions. In exemplary applications, such techniques are used for debugging graphics processors of wireless communication system-on-chip devices, among other programmable integrated circuit devices.

摘要翻译： 描述了用于调试可编程集成电路的技术。 实施例包括使用执行测试程序的远程计算机启动集成电路中的指令高速缓存未命中的步骤; 在指令高速缓存未命中事件期间，使用测试程序提供的测试指令来代替应用程序中的指令; 并根据其对测试指令的响应分析调试集成电路。 在示例性应用中，这样的技术用于调试无线通信片上系统的图形处理器以及其他可编程集成电路器件。

公开(公告)号：US08533530B2

公开(公告)日：2013-09-10

申请号：US11560332

申请日：2006-11-15

申请人： Lucian Codrescu ,  William C. Anderson ,  Suresh Venkumahanti ,  Louis Achille Giannini ,  Manojkumar Pyla ,  Xufeng Chen

发明人： Lucian Codrescu ,  William C. Anderson ,  Suresh Venkumahanti ,  Louis Achille Giannini ,  Manojkumar Pyla ,  Xufeng Chen

IPC分类号： G06F11/00

CPC分类号： G06F11/3656

摘要： Techniques for the design and use of a digital signal processor, including (but not limited to) for processing transmissions in a communications (e.g., CDMA) system. Trusted and untrusted debugging operational control occurs in operating a core processor associated with the digital signal processor. A debugging process within a debugging mechanism associates with the core processor. The core processor process determines the origin of debugging control as trusted debugging control or untrusted debugging control. In the event of trusted debugging control, the core processor process provides to the trusted debugging control a first set of features and privileges. Alternatively, in the event that debugging control is untrusted debugging control, the core processor process provides the untrusted debugging control a second restricted set of features and privileges, all for maintaining security and proper operation of the core processor process.

摘要翻译： 用于设计和使用数字信号处理器的技术，包括（但不限于）用于处理通信（例如，CDMA）系统中的传输。 在操作与数字信号处理器相关联的核心处理器时，发生信任和不信任的调试操作控制。 调试机制中的调试过程与核心处理器相关联。 核心处理器过程将调试控制的起源确定为可信的调试控制或不可信的调试控制。 在受信任的调试控制的情况下，核心处理器进程向受信任的调试控制提供了第一组功能和特权。 或者，如果调试控制是不可信任的调试控制，则核心处理器进程将不可信任的调试控制提供第二个受限制的特征和特权集，以保持核心处理器进程的安全性和正常运行。

公开(公告)号：US20120047402A1

公开(公告)日：2012-02-23

申请号：US12861171

申请日：2010-08-23

申请人： Xufeng Chen ,  Peixin Zhong ,  Manojkumar Pyla

发明人： Xufeng Chen ,  Peixin Zhong ,  Manojkumar Pyla

IPC分类号： G06F11/00 ,  G06F13/24

CPC分类号： G06F1/3203 ,  G06F1/3287 ,  G06F13/24 ,  Y02D10/171 ,  Y02D50/20

摘要： In a particular embodiment, a method of monitoring interrupts during a power down event at a processor includes activating an interrupt monitor to detect interrupts. The method also includes isolating an interrupt controller of the processor from the interrupt monitor, where the interrupt controller shares a power domain with the processor. The method also includes detecting interrupts at the interrupt monitor during a power down time period associated with the power down event.

摘要翻译： 在特定实施例中，在处理器的断电事件期间监视中断的方法包括激活中断监视器以检测中断。 该方法还包括将中断控制器与中断监视器隔离，其中中断控制器与处理器共享一个电源域。 该方法还包括在与断电事件相关联的掉电时间段期间检测中断监视器处的中断。