公开(公告)号：US06884335B2

公开(公告)日：2005-04-26

申请号：US10441607

申请日：2003-05-20

Applicant: Eric G. Webb ,  Jonathan D. Reid ,  John H. Sukamto ,  Sesha Varadarajan ,  Margolita M. Pollack ,  Bryan L. Buckalew ,  Tariq Majid

Inventor： Eric G. Webb ,  Jonathan D. Reid ,  John H. Sukamto ,  Sesha Varadarajan ,  Margolita M. Pollack ,  Bryan L. Buckalew ,  Tariq Majid

IPC: C25D5/04 ,  C25D5/18 ,  C25D7/12 ,  H01L21/288

CPC classification number: C25D5/04 ,  C25D5/18 ,  C25D7/123 ,  C25D17/001 ,  H01L21/2885 ,  Y10S428/935 ,  Y10T428/12993

Abstract: A negative bias is applied to an integrated circuit wafer immersed in an electrolytic plating solution to generate a DC current. After about ten percent to sixty percent of the final layer thickness has formed in a first plating time, biasing is interrupted during short pauses during a second plating time to generate substantially zero DC current. The pauses are from about 2 milliseconds to 5 seconds long, and typically about 10 milliseconds to 500 milliseconds. Generally, about 2 pauses to 100 pauses are used, and typically about 3 pauses to 15 pauses. Generally, the DC current density during the second plating time is greater than the DC current density during the initial plating time. Typically, the integrated circuit wafer is rotated during electroplating. Preferably, the wafer is rotated at a slower rotation rate during the second plating time than during the first plating time.

Abstract translation: 将负偏压施加到浸在电解电镀溶液中的集成电路晶片以产生DC电流。 在第一电镀时间中已经形成最终层厚度的约百分之十到百分之六十之后，在第二电镀时间期间的短暂停期间偏压中断，以产生基本为零的DC电流。 停顿时间为大约2毫秒到5秒，通常为大约10毫秒到500毫秒。 通常，使用约2次暂停至100次暂停，通常约3次暂停至15次停顿。 通常，第二电镀时间期间的直流电流密度大于初始电镀时间期间的直流电流密度。 通常，电镀期间集成电路晶片旋转。 优选地，在第二电镀时间期间，晶片以比第一电镀时间期间更慢的旋转速度旋转。