Abstract:
A method of forming a transistor is disclosed that comprises the step forming a gate insulator layer 12 on an outer surface of the substrate 10. A first gate conductor layer 22 is formed outwardly from the gate insulator layer 12. The first gate conductor layer 22 is extremely thin. Dopants are introduced into the layer 22 to render it conductive by using a diffusion source layer 24. The diffusion source layer 24 is then removed and replaced by a second gate conductor layer 26 having low resistance. The layer 26 can be used to form a T-gate structure 28, a flush gate 30, or a conventional gate structure.
Abstract:
Methods of forming strain-relaxing semiconductor layers are provided in which a porous region is formed in a surface of a semiconductor substrate. A first semiconductor layer that is lattice-matched with the semiconductor substrate is formed on the porous region. A second semiconductor layer is formed on the first semiconductor layer, the second semiconductor layer being a strained layer as formed. The second semiconductor layer is then relaxed.
Abstract:
Methods of forming strain-relaxing semiconductor layers are provided in which a porous region is formed in a surface of a semiconductor substrate. A first semiconductor layer that is lattice-matched with the semiconductor substrate is formed on the porous region. A second semiconductor layer is formed on the first semiconductor layer, the second semiconductor layer being a strained layer as formed. The second semiconductor layer is then relaxed.