公开(公告)号：US06303923B1

公开(公告)日：2001-10-16

申请号：US09437328

申请日：1999-11-09

申请人： Mark Wadsworth ,  Gene Atlas

发明人： Mark Wadsworth ,  Gene Atlas

IPC分类号： H01J4014

CPC分类号： H01L27/14634

摘要： A hybrid detector or imager includes two substrates fabricated under incompatible processes. An array of detectors, such as charged-coupled devices, are formed on the first substrate using a CCD fabrication process, such as a buried channel or peristaltic process. One or more charge-converting amplifiers are formed on a second substrate using a CMOS fabrication process. The two substrates are then bonded together to form a hybrid detector.

摘要翻译： 混合检测器或成像器包括在不相容的工艺下制造的两个基片。 使用诸如掩埋通道或蠕动过程的CCD制造工艺在第一基板上形成诸如电荷耦合器件的检测器阵列。 使用CMOS制造工艺在第二衬底上形成一个或多个电荷转换放大器。 然后将两个基板结合在一起以形成混合检测器。

公开(公告)号：US5189423A

公开(公告)日：1993-02-23

申请号：US784277

申请日：1991-10-29

申请人： Thomas E. Linnenbrink ,  Mark Wadsworth ,  Stephen D. Gaalema

发明人： Thomas E. Linnenbrink ,  Mark Wadsworth ,  Stephen D. Gaalema

IPC分类号： H03M1/12 ,  H03M1/44

CPC分类号： H03M1/1235 ,  H03M1/44

摘要： A symmetric pipelined charge-mode analog to digital converter including a signal-reference CCD channel having a plurality of charge storage stages that are arranged in a serial configuration to carry the signal and reference charges, and a CCD digital channel. A set of two step comparators coupled to the signal-reference channel first senses and stores the signal charge and then senses and compares the reference charge to the signal charge. In the first stage, an initial reference charge is used, and in subsequeant stages, an increment of one half the previous stage increment is added to the reference. In addition, at each stage, a charge increment equal to the previous reference increment is conditionally added to the signal charge and a corresponding bit in the digital channel is conditionally set responsive to the comparator. Thus, if the total signal charge is less than the total reference charge at a stage, the charge increment is added to the signal charge in the signal-reference channel, and a corresponding digital bit charge is zeroed in the digital channel. Conversely, if the total signal charge is larger than the told reference charge at a stage, the charge increment is not added to the signal charge and a corresponding digital bit charge is set to represent a one in the digital channel. One configuration provides a differential symmetric architecture wherein two signal-reference channels simultaneously feed a dual symmetric comparator providing enhanced symmetry thereby reducing threshold and offset sensitivity and susceptibility to environmental factors such as ionizing radiation.

摘要翻译： 一种对称流水线充电模式模数转换器，包括具有多个电荷存储级的信号参考CCD通道，该多个电荷存储级以串行配置布置以承载信号和参考电荷，以及CCD数字通道。 耦合到信号参考通道的一组两级比较器首先感测并存储信号电荷，然后感测并比较参考电荷与信号电荷。 在第一阶段，使用初始参考电荷，并且在辅助级中，将前一级增量的一半的增量添加到引用。 此外，在每个阶段，等价于先前参考增量的电荷增量被有条件地加到信号电荷上，并且响应于比较器有条件地设置数字信道中的相应位。 因此，如果总信号电荷小于一级的总参考电荷，则将电荷增量添加到信号参考通道中的信号电荷，并且相应的数字位电荷在数字通道中归零。 相反，如果总信号电荷大于一级的告知参考电荷，则不向信号电荷添加电荷增量，并且将相应的数字位电荷设置为在数字通道中表示一个。 一种配置提供了一种差分对称架构，其中两个信号参考通道同时馈送双对称比较器，提供增强的对称性，从而降低阈值和偏移灵敏度以及对诸如电离辐射的环境因素的敏感性。

公开(公告)号：US08164121B2

公开(公告)日：2012-04-24

申请号：US12780708

申请日：2010-05-14

申请人： Mark Wadsworth

发明人： Mark Wadsworth

IPC分类号： H01L27/148

CPC分类号： H01L27/14683 ,  H01L27/1462 ,  H01L27/14806 ,  H01L27/1485

摘要： A six-phase charge coupled device (CCD) pixel includes a pixel pair, with each pixel having two adjacent control gates overlying corresponding variable potential wells, where voltages applied to the control gates enable charge to be accumulated into and transferred out of the wells. A clear window region overlies a fixed potential gradient region, decreasing in potential away from the control gates. This region enables a wide band of photons to be sensed by the photosensitive silicon of the CCD. The decreasing potential levels facilitate high charge transfer efficiency (i.e., high CTE) from pixel to pixel via the control or transfer gates. By applying particular voltages to the control gates, charge can be quickly and efficiently transferred between pixels. In addition, the window provides a self aligned mask for the implantation steps and thus prevents the formation of pockets (or wells) due to misalignments that decrease the charge transfer efficiency and causes non-uniformity problems as associated with prior art. Furthermore the window provides a flat region that can be covered with an anti-reflective (AR) coating layer, thus further increasing the quantum efficiency.

摘要翻译： 六相电荷耦合器件（CCD）像素包括像素对，其中每个像素具有覆盖相应的可变势阱的两个相邻的控制栅极，其中施加到控制栅极的电压使得电荷能够积累并输出到阱中。 清晰的窗口区域覆盖固定的电位梯度区域，电位远离控制栅极减小。 该区域使得能够通过CCD的感光硅感测宽带光子。 降低的电位电平有助于通过控制或传输门从像素到像素的高电荷转移效率（即高CTE）。 通过对控制栅极施加特定的电压，可以在像素之间快速有效地传送电荷。 此外，窗口为植入步骤提供自对准的掩模，并且因此防止由于未对准而导致的口袋（或孔）的形成，这会降低电荷转移效率并引起与现有技术相关的不均匀性问题。 此外，窗口提供可以用抗反射（AR）涂层覆盖的平坦区域，从而进一步增加量子效率。

公开(公告)号：US5923061A

公开(公告)日：1999-07-13

申请号：US880207

申请日：1997-06-23

申请人： Thomas E. Linnenbrink ,  Mark Wadsworth ,  Stephen D. Gaalema

发明人： Thomas E. Linnenbrink ,  Mark Wadsworth ,  Stephen D. Gaalema

IPC分类号： H01L29/762 ,  G11C19/28 ,  H01L21/339 ,  H01L27/148 ,  H03M1/06 ,  H03M1/12 ,  H01L29/768

CPC分类号： H03M1/0658 ,  G11C19/282 ,  H01L27/148 ,  H03M1/12

摘要： An apparatus and method of equalizing a first and second charge packet. The apparatus includes a charge splitter for splitting the first charge packet into a third charge packet on the first side of the charge splitter and a fourth charge packet on the second side of the charge splitter. The second charge component is split into a fifth charge component on the first side of the charge splitter and a sixth charge component on the second side of the charge splitter. The apparatus includes a charge combiner for adding the third and sixth charge packets and the fourth and fifth charge packets.

摘要翻译： 一种均衡第一和第二充电包的装置和方法。 该装置包括电荷分配器，用于将第一充电分组分裂成电荷分配器的第一侧上的第三充电分组，以及在分离器的第二侧上的第四充电分组。 第二电荷分量在电荷分配器的第一侧被分成第五电荷分量，并且在电荷分离器的第二侧被分成第六电荷分量。 该装置包括用于添加第三和第六充电分组以及第四和第五充电分组的电荷组合器。

公开(公告)号：US5708282A

公开(公告)日：1998-01-13

申请号：US511655

申请日：1995-08-07

申请人： Thomas E. Linnenbrink ,  Mark Wadsworth ,  Stephen D. Gaalema

发明人： Thomas E. Linnenbrink ,  Mark Wadsworth ,  Stephen D. Gaalema

IPC分类号： H01L29/762 ,  G11C19/28 ,  H01L21/339 ,  H01L27/148 ,  H03M1/06 ,  H03M1/12 ,  H01L29/768

CPC分类号： H03M1/0658 ,  G11C19/282 ,  H01L27/148 ,  H03M1/12

摘要： An apparatus and method of equalizing a first and second charge packet. The apparatus includes a charge splitter for splitting the first charge packet into a third charge packet on the first side of the charge splitter and a fourth charge packet on the second side of the charge splitter. The second charge component is split into a fifth charge component on the first side of the charge splitter and a sixth charge component on the second side of the charge splitter. The apparatus includes a charge combinet for adding the third and sixth charge packets and the fourth and fifth charge packets.

摘要翻译： 一种均衡第一和第二充电包的装置和方法。 该装置包括电荷分配器，用于将第一充电分组分裂成电荷分配器的第一侧上的第三充电分组，以及在分离器的第二侧上的第四充电分组。 第二电荷分量在电荷分配器的第一侧被分成第五电荷分量，并且在电荷分离器的第二侧被分成第六电荷分量。 该装置包括用于添加第三和第六充电分组以及第四和第五充电分组的充电组合。

公开(公告)号：US20100258847A1

公开(公告)日：2010-10-14

申请号：US12780708

申请日：2010-05-14

申请人： Mark Wadsworth

发明人： Mark Wadsworth

IPC分类号： H01L27/148

CPC分类号： H01L27/14683 ,  H01L27/1462 ,  H01L27/14806 ,  H01L27/1485

摘要： A six-phase charge coupled device (CCD) pixel includes a pixel pair, with each pixel having two adjacent control gates overlying corresponding variable potential wells, where voltages applied to the control gates enable charge to be accumulated into and transferred out of the wells. A clear window region overlies a fixed potential gradient region, decreasing in potential away from the control gates. This region enables a wide band of photons to be sensed by the photosensitive silicon of the CCD. The decreasing potential levels facilitate high charge transfer efficiency (i.e., high CTE) from pixel to pixel via the control or transfer gates. By applying particular voltages to the control gates, charge can be quickly and efficiently transferred between pixels. In addition, the window provides a self aligned mask for the implantation steps and thus prevents the formation of pockets (or wells) due to misalignments that decrease the charge transfer efficiency and causes non-uniformity problems as associated with prior art. Furthermore the window provides a flat region that can be covered with an anti-reflective (AR) coating layer, thus further increasing the quantum efficiency.

摘要翻译： 六相电荷耦合器件（CCD）像素包括像素对，其中每个像素具有覆盖相应的可变势阱的两个相邻的控制栅极，其中施加到控制栅极的电压使得电荷能够积累并输出到阱中。 清晰的窗口区域覆盖固定的电位梯度区域，电位远离控制栅极减小。 该区域使得能够通过CCD的感光硅感测宽带光子。 降低的电位电平有助于通过控制或传输门从像素到像素的高电荷转移效率（即高CTE）。 通过对控制栅极施加特定的电压，可以在像素之间快速有效地传送电荷。 此外，窗口为植入步骤提供自对准的掩模，并且因此防止由于未对准而导致的口袋（或孔）的形成，这会降低电荷转移效率并引起与现有技术相关的不均匀性问题。 此外，窗口提供可以用抗反射（AR）涂层覆盖的平坦区域，从而进一步增加量子效率。

公开(公告)号：US20060238635A1

公开(公告)日：2006-10-26

申请号：US11450777

申请日：2006-06-09

申请人： Gene Atlas ,  Mark Wadsworth ,  Richard Kullman ,  Sarit Neter

发明人： Gene Atlas ,  Mark Wadsworth ,  Richard Kullman ,  Sarit Neter

IPC分类号： H04N5/335

CPC分类号： G11C19/285 ,  H01L27/14625 ,  H01L27/14806 ,  H01L27/1485 ,  H01L29/76816 ,  H04N5/357 ,  H04N5/372 ,  H04N5/37213 ,  H04N5/3725 ,  H04N5/378

摘要： A charge coupled device (CCD) includes a low noise charge gain circuit that amplifies charge of a cell dependent upon the charge accumulated by the cell. The low noise charge gain circuit receives clocking signals, such as from an input diode, which allow charge to accumulate in a reservoir well and then flow into a receiving well. The low noise charge gain circuit also receives a voltage signal corresponding to charge accumulated on an associated cell. The amount of charge flowing into the receiving well depends on this voltage signal.

摘要翻译： 电荷耦合器件（CCD）包括低噪声电荷增益电路，其根据该单元累积的电荷来放大单元的电荷。 低噪声充电增益电路接收时钟信号，例如来自输入二极管，其允许电荷积聚在储层中，然后流入接收阱。 低噪声充电增益电路还接收对应于在相关联的单元上累积的电荷的电压信号。 流入接收阱的电荷量取决于该电压信号。

公开(公告)号：US06590197B2

公开(公告)日：2003-07-08

申请号：US09978621

申请日：2001-10-15

申请人： Mark Wadsworth ,  Gene Atlas

发明人： Mark Wadsworth ,  Gene Atlas

IPC分类号： H01L2700

CPC分类号： H01L27/14634

摘要： A hybrid detector or imager includes two substrates fabricated under incompatible processes. An array of detectors, such as charged-coupled devices, are formed on the first substrate using a CCD fabrication process, such as a buried channel or peristaltic process. One or more charge-converting amplifiers are formed on a second substrate using a CMOS fabrication process. The two substrates are then bonded together to form a hybrid detector.

公开(公告)号：US08829409B2

公开(公告)日：2014-09-09

申请号：US13648741

申请日：2012-10-10

申请人： Mark Wadsworth

发明人： Mark Wadsworth

IPC分类号： H01L27/00 ,  H04N3/14

CPC分类号： G01J1/46 ,  G01J1/44

摘要： A plurality of unit pixels in a two dimensional imaging array are arranged in a manner that signal charges along a given row are added to other relevant signal charges of the same row. Signal charges along a given column are added to other relevant signal charges of the same column. Summed charge values are output simultaneously from rows and columns to produce one row and one column of image data. The resulting summed data is temporarily stored in on-chip buffers and then output from the chip during the integration time of the next imaging cycle with no loss in imaging duty cycle.

摘要翻译： 二维成像阵列中的多个单位像素被布置成使得沿着给定行的信号电荷被添加到同一行的其它相关信号电荷的方式。 沿给定列的信号电荷被添加到同一列的其他相关信号电荷。 累加电荷值从行和列同时输出，以产生一行和一列图像数据。 所得到的求和数据被临时存储在片上缓冲器中，然后在下一个成像周期的积分时间期间从芯片输出，而没有成像占空比的损失。

公开(公告)号：US20140097329A1

公开(公告)日：2014-04-10

申请号：US13648741

申请日：2012-10-10

申请人： Mark WADSWORTH

发明人： Mark WADSWORTH

IPC分类号： H01L27/146

CPC分类号： G01J1/46 ,  G01J1/44

摘要： A plurality of unit pixels in a two dimensional imaging array are arranged in a manner that signal charges along a given row are added to other relevant signal charges of the same row. Signal charges along a given column are added to other relevant signal charges of the same column. Summed charge values are output simultaneously from rows and columns to produce one row and one column of image data. The resulting summed data is temporarily stored in on-chip buffers and then output from the chip during the integration time of the next imaging cycle with no loss in imaging duty cycle.

摘要翻译： 二维成像阵列中的多个单位像素被布置成使得沿着给定行的信号电荷被添加到同一行的其它相关信号电荷的方式。 沿给定列的信号电荷被添加到同一列的其他相关信号电荷。 累加电荷值从行和列同时输出，以产生一行和一列图像数据。 所得到的求和数据被临时存储在片上缓冲器中，然后在下一个成像周期的积分时间期间从芯片输出，而没有成像占空比的损失。