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公开(公告)号：US07174442B2
公开(公告)日：2007-02-06
申请号：US10432203
申请日：2001-11-21
申请人： John Lancaster , Martin Whitaker
发明人： John Lancaster , Martin Whitaker
IPC分类号： G06F12/00
CPC分类号： G06F9/30043 , G06F9/345 , G06F13/28
摘要： A method of carrying out a data fetch operation for a data-parallel processor such as a SIMD processor is described. The operation is specifically involving the use of a plurality of non-sequential data addresses. The method comprises constructing a linear address vector from the non-sequential addresses, and using the address vector in a block fetch command to a data store.
摘要翻译： 描述了对诸如SIMD处理器之类的数据并行处理器执行数据提取操作的方法。 该操作具体涉及使用多个非顺序数据地址。 该方法包括从非顺序地址构建线性地址向量，并且使用块获取命令中的地址向量到数据存储。
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公开(公告)号：US20120047350A1
公开(公告)日：2012-02-23
申请号：US13318404
申请日：2010-05-04
申请人： John Lancaster , Martin Whitaker
发明人： John Lancaster , Martin Whitaker
CPC分类号： G06F8/45 , G06F9/3887 , G06F9/3889 , G06F15/8015
摘要： A processing apparatus for processing source code comprising a plurality of single line instructions to implement a desired processing function is described. The processing apparatus comprises:i) a string-based non-associative multiple—SIMD (Single Instruction Multiple Data) parallel processor arranged to process a plurality of different instruction streams in parallel, the processor including: a plurality of data processing elements connected sequentially in a string topology and organised to operate in a multiple—SIMD configuration, the data processing elements being arranged to be selectively and independently activated to take part in processing operations, and a plurality of SIMD controllers, each connectable to a group of selected data processing elements of the plurality of data processing elements for processing a specific instruction stream, each group being defined dynamically during run-time by a single line instruction provided in the source code, andii) a compiler for verifying and converting the plurality of the single line instructions into an executable set of commands for the parallel processor, wherein the processing apparatus is arranged to process each single line instruction which specifies an operation and an active group of selected data processing elements for each SIMD controller that is to take part in the operation.
摘要翻译： 描述了一种用于处理源代码的处理装置，该处理装置包括多条单行指令以实现期望的处理功能。 该处理装置包括：i）基于串的非关联多SIMD（单指令多数据）并行处理器，其被并行处理多个不同的指令流，所述处理器包括：多个数据处理单元， 字符串拓扑并被组织以在多SIMD配置中操作，所述数据处理元件被布置为选择性地和独立地激活以参与处理操作;以及多个SIMD控制器，每个SIMD控制器可连接到一组选择的数据处理元件 用于处理特定指令流的多个数据处理元件中，每个组在运行期间通过在源代码中提供的单行指令动态地定义，以及ii）用于验证和转换多条单行指令的编译器 转换成用于并行处理器的可执行命令集，其中处理 装置被设置为处理指定用于参与该操作的每个SIMD控制器的操作的选定数据处理元件的活动组的每个单行指令。
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3.发明授权Scalable processing network for searching and adding in a content addressable memory 有权可扩展处理网络，用于搜索和添加内容可寻址存储器公开(公告)号：US07865662B2
公开(公告)日：2011-01-04
申请号：US10539493
申请日：2003-12-17
CPC分类号： G06F15/8038
摘要： An alternation network for use with a content addressable memory for implementing a divide and conquer algorithm is described. The alternation network comprises: a plurality of alternation modules connected in series together, each module comprising: a plurality of cascaded logic gates arranged to propagate a match parity signal via the gates along at least part of a matching result vector, the matching result vector being generated by execution of a matching instruction on the content addressable memory, and the logic gates being configured to change the parity of the match parity signal in accordance with the matching result vector; and a vector output arranged to output a parity level vector of the propagated match parity signal present at the each gate of the plurality of logic gates; a logic network for dividing the matching result vector into an odd match vector and an even match vector representing respectively odd and even numbered elements of the matching result vector, by use of the parity level vector, and means for writing a selected one of the odd and even match vectors to the content addressable memory.
摘要翻译： 描述了用于实现分割和征服算法的内容可寻址存储器的交替网络。 所述交替网络包括：串联连接的多个交替模块，每个模块包括：多个级联逻辑门，布置成沿着匹配结果向量的至少一部分经由所述门传播匹配奇偶校验信号，所述匹配结果向量为 通过在内容可寻址存储器上执行匹配指令而产生，并且逻辑门被配置为根据匹配结果向量改变匹配奇偶校验信号的奇偶校验; 以及矢量输出，被布置为输出存在于所述多个逻辑门的每个门处的所传播的匹配奇偶校验信号的奇偶校验电平矢量; 用于通过使用奇偶校验电平矢量将匹配结果矢量划分为奇数匹配向量和偶数匹配向量，表示分别为奇数和偶数编号的匹配结果向量元素的偶数向量;以及用于写入奇数 甚至将向量匹配到内容可寻址存储器。
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4.发明申请Scalable processing network for searching and adding in a content addressable memory 有权可扩展处理网络，用于搜索和添加内容可寻址存储器公开(公告)号：US20060184689A1
公开(公告)日：2006-08-17
申请号：US10539493
申请日：2003-12-17
IPC分类号： G06F15/173
CPC分类号： G06F15/8038
摘要： An alternation network for use with a content addressable memory for implementing a divide and conquer algorithm is described. The alternation network comprises: a plurality of alternation modules connected in series together, each module comprising: a plurality of cascaded logic gates arranged to propagate a match parity signal via the gates along at least part of a matching result vector, the matching result vector being generated by execution of a matching instruction on the content addressable memory, and the logic gates being configured to change the parity of the match parity signal in accordance with the matching result vector; and a vector output arranged to output a parity level vector of the propagated match parity signal present at the each gate of the plurality of logic gates; a logic network for dividing the matching result vector into an odd match vector and an even match vector representing respectively odd and even numbered elements of the matching result vector, by use of the parity level vector, and means for writing a selected one of the odd and even match vectors to the content addressable memory.
摘要翻译： 描述了用于实现分割和征服算法的内容可寻址存储器的交替网络。 所述交替网络包括：串联连接的多个交替模块，每个模块包括：多个级联逻辑门，布置成沿着匹配结果向量的至少一部分经由所述门传播匹配奇偶校验信号，所述匹配结果向量为 通过在内容可寻址存储器上执行匹配指令而产生，并且逻辑门被配置为根据匹配结果向量改变匹配奇偶校验信号的奇偶校验; 以及矢量输出，被布置为输出存在于所述多个逻辑门的每个门处的所传播的匹配奇偶校验信号的奇偶校验电平矢量; 用于通过使用奇偶校验电平矢量将匹配结果矢量划分为奇数匹配向量和偶数匹配向量，表示分别为奇数和偶数编号的匹配结果向量元素的偶数向量;以及用于写入奇数 甚至将向量匹配到内容可寻址存储器。
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5.发明授权Parallel processor with single instruction multiple data (SIMD) controllers 有权具有单指令多数据（SIMD）控制器的并行处理器公开(公告)号：US09195467B2
公开(公告)日：2015-11-24
申请号：US12993793
申请日：2009-05-20
申请人： John Lancaster , Martin Whitaker
发明人： John Lancaster , Martin Whitaker
CPC分类号： G06F9/3887 , G06F9/3016 , G06F9/3889 , G06F9/3891 , G06F15/8007
摘要： Improvements Relating to Single Instruction Multiple Data (SIMD) Architectures A parallel processor for processing a plurality of different processing instruction streams in parallel is described. The processor comprises a plurality of data processing units; and a plurality of SIMD (Single Instruction Multiple Data) controllers, each connectable to a group of data processing units of the plurality of data processing units, and each SIMD controller arranged to handle an individual processing task with a subgroup of actively connected data processing units selected from the group of data processing units. The parallel processor is arranged to vary dynamically the size of the subgroup of data processing units to which each SIMD controller is actively connected under control of received processing instruction streams, thereby permitting each SIMD controller to be actively connected to a different number of processing units for different processing tasks.
摘要翻译： 关于单指令多数据（SIMD）架构的改进描述了并行处理多个不同处理指令流的并行处理器。 处理器包括多个数据处理单元; 以及多个SIMD（单指令多数据）控制器，每个SIMD（单指令多数据）控制器可连接到多个数据处理单元的一组数据处理单元，并且每个SIMD控制器被布置成处理具有主动连接的数据处理单元的子组的单独处理任务 从数据处理单元组中选择。 并行处理器被布置为在接收到的处理指令流的控制下动态地改变每个SIMD控制器主动连接到的数据处理单元的子组的大小，从而允许每个SIMD控制器主动地连接到不同数量的处理单元 不同的处理任务。
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公开(公告)号：US20110191567A1
公开(公告)日：2011-08-04
申请号：US12993793
申请日：2009-05-20
申请人： John Lancaster , Martin Whitaker
发明人： John Lancaster , Martin Whitaker
IPC分类号： G06F9/30
CPC分类号： G06F9/3887 , G06F9/3016 , G06F9/3889 , G06F9/3891 , G06F15/8007
摘要： Improvements Relating to Single Instruction Multiple Data (SIMD) Architectures A parallel processor for processing a plurality of different processing instruction streams in parallel is described. The processor comprises a plurality of data processing units; and a plurality of SIMD (Single Instruction Multiple Data) controllers, each connectable to a group of data processing units of the plurality of data processing units, and each SIMD controller arranged to handle an individual processing task with a subgroup of actively connected data processing units selected from the group of data processing units. The parallel processor is arranged to vary dynamically the size of the subgroup of data processing units to which each SIMD controller is actively connected under control of received processing instruction streams, thereby permitting each SIMD controller to be actively connected to a different number of processing units for different processing tasks.
摘要翻译： 关于单指令多数据（SIMD）架构的改进描述了并行处理多个不同处理指令流的并行处理器。 处理器包括多个数据处理单元; 以及多个SIMD（单指令多数据）控制器，每个SIMD（单指令多数据）控制器可连接到多个数据处理单元的一组数据处理单元，并且每个SIMD控制器被布置成处理具有主动连接的数据处理单元的子组的单独处理任务 从数据处理单元组中选择。 并行处理器被布置为在接收到的处理指令流的控制下动态地改变每个SIMD控制器主动连接到的数据处理单元的子组的大小，从而允许每个SIMD控制器主动地连接到不同数量的处理单元 不同的处理任务。
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公开(公告)号：US20110185151A1
公开(公告)日：2011-07-28
申请号：US12993801
申请日：2009-05-20
申请人： Martin Whitaker , John Lancaster
发明人： Martin Whitaker , John Lancaster
CPC分类号： G06F15/8015
摘要： A parallel processor is described which is operated in a SIMD manner. The processor comprises: a plurality of processing elements connected in a string and grouped into a plurality of processing units, wherein each processing unit comprises a plurality of processing elements which each have direct interconnections with all of the other processing elements within the respective processing unit, the interconnections enabling data transfer between any two elements within a unit to be effected in a single clock cycle.
摘要翻译： 描述了以SIMD方式操作的并行处理器。 处理器包括：串联连接并分组成多个处理单元的多个处理元件，其中每个处理单元包括多个处理元件，每个处理元件与相应处理单元内的所有其它处理元件具有直接互连， 能够在单个时钟周期内实现单元内的任何两个元件之间的数据传输的互连。
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公开(公告)号：US20240035629A1
公开(公告)日：2024-02-01
申请号：US18167162
申请日：2023-02-10
申请人： John Lancaster
发明人： John Lancaster
CPC分类号： F17D5/02 , F17C13/08 , F17C2221/032 , F17C2260/028 , F17C2270/0134
摘要： The present invention relates to a fuel oil theft prevention tool configured to prevent theft or siphoning of fuel oil from a fuel tank. The tool is compact and lightweight and includes a metal female×female reduced coupling, a heavy-duty metal screen having a plurality of holes disposed therein, the screen is positioned inside the reduced coupling and is secured/biased and held tight by a torsional spring, a male×female hex bushing having a hexagonal head is positioned inside the reduced coupling over the screen for further securing of the screen. The tool is positioned between the fuel delivery pipe and the supply pipe and is configured to allow flow of fuel oil in only one direction.
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公开(公告)号：US07096318B2
公开(公告)日：2006-08-22
申请号：US10432307
申请日：2001-11-21
IPC分类号： G06F13/28
摘要： A compound associative memory for use with a data-parallel computer, and a method of storing/retrieving data in the compound associative memory is disclosed. The memory comprises a bit-parallel word-organized associative memory having an array of associative memory cells arranged to be capable of bit-parallel search and write operations. A bit-serial associative memory having an array of memory cells arranged to be capable of bit-serial search and write operations, but not word bit-parallel search and write operations, is also included. The bit-serial memory is operatively connected to the bit-parallel memory and arranged to operate as an extension of the same. The method comprises searching the bit-parallel word-organized associative memory and/or the bit-serial associative memory coupled to the bit-parallel memory for data matching search data, and marking the memory cells having stored data matching the search data.
摘要翻译： 公开了一种与数据并行计算机一起使用的复合关联存储器，以及在复合关联存储器中存储/检索数据的方法。 存储器包括位并行字组织的关联存储器，其具有布置成能够进行位并行搜索和写入操作的关联存储器单元的阵列。 还包括具有布置成能够进行位串行搜索和写入操作而不是字位并行搜索和写入操作的存储器单元阵列的位串行关联存储器。 位串行存储器可操作地连接到比特并行存储器并且被布置为作为其扩展来操作。 该方法包括搜索与并行存储器耦合的位并行字组织关联存储器和/或位串联相关存储器，用于搜索数据匹配，以及标记具有与搜索数据匹配的存储数据的存储器单元。
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10.发明授权Method and apparatus for conversion of the sampled signal of an analog input signal 失效用于转换模拟输入信号的采样信号的方法和装置
公开(公告)号：US5148169A
公开(公告)日：1992-09-15
申请号：US663844
申请日：1991-05-20
摘要： A method for converting a sampled signal of an analog input signal to a digital output signal that is L data bits in length is provided. The method includes the steps of: a) converting the sampled signal to a digital reference signal of M
摘要翻译： 提供一种用于将模拟输入信号的采样信号转换为长度为L个数据位的数字输出信号的方法。 该方法包括以下步骤：a）仅在作为工作周期的一部分的采样周期期间将采样信号转换为M
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