公开(公告)号：US06509786B2

公开(公告)日：2003-01-21

申请号：US09968003

申请日：2001-10-02

申请人： Masaki Uekubo

发明人： Masaki Uekubo

IPC分类号： G05F110

CPC分类号： G05F3/205 ,  G11C16/26 ,  G11C16/28

摘要： A biasing circuit includes an increasing circuit, a supplying circuit, a bias outputting circuit and a bias outputting circuit. The increasing circuit outputs a drive voltage, and the supplying circuit is connected in parallel to the increasing circuit and outputs a drive voltage. The bias outputting circuit outputs a bias output to a biased circuit in response to the drive voltage from the increasing circuit or the drive voltage from the supplying circuit. The control circuit controls the increasing circuit and the supplying circuit based on the bias output from the bias outputting circuit.

公开(公告)号：US06323724B1

公开(公告)日：2001-11-27

申请号：US09447589

申请日：1999-11-23

申请人： Masaki Uekubo

发明人： Masaki Uekubo

IPC分类号： G05F110

CPC分类号： G05F3/205 ,  G11C16/26 ,  G11C16/28

摘要： A biasing circuit includes an increasing circuit, a supplying circuit, a bias outputting circuit and a bias outputting circuit. The increasing circuit outputs a drive voltage, and the supplying circuit is connected in parallel to the increasing circuit and outputs a drive voltage. The bias outputting circuit outputs a bias output to a biased circuit in response to the drive voltage from the increasing circuit or the drive voltage from the supplying circuit. The control circuit controls the increasing circuit and the supplying circuit based on the bias output from the bias outputting circuit.

摘要翻译： 偏置电路包括增加电路，供电电路，偏置输出电路和偏置输出电路。 增加的电路输出驱动电压，并且供电电路并联连接到增加电路并输出驱动电压。 偏置输出电路响应于来自增加电路的驱动电压或来自供电电路的驱动电压而将偏置输出输出到偏置电路。 控制电路基于来自偏置输出电路的偏置输出来控制增加电路和供电电路。

公开(公告)号：US08531963B2

公开(公告)日：2013-09-10

申请号：US12663474

申请日：2008-05-30

申请人： Hiroaki Inoue ,  Masamichi Takagi ,  Masaki Uekubo ,  Sunao Torii ,  Masato Edahiro

发明人： Hiroaki Inoue ,  Masamichi Takagi ,  Masaki Uekubo ,  Sunao Torii ,  Masato Edahiro

IPC分类号： H04J3/14

CPC分类号： H04L63/0263 ,  G06F15/7825 ,  H04L63/0218

摘要： A semiconductor integrated circuit of the invention comprises a plurality of cores, and an interconnecting network including adaptors connected to each of the cores and a plurality of routers connecting the adaptors to communicate therebetween. Transmission side adaptors store first delivery information, and control delivery of the request signal to be received from the first core in accordance with the first delivery information. Reception side adaptors store second delivery information, and control delivery of the request signal to be received through the interconnecting network to the second core in accordance with the second delivery information. The first delivery information and the second delivery information are hierarchically set.

摘要翻译： 本发明的半导体集成电路包括多个核心，以及包括连接到每个核心的适配器的互连网络以及连接适配器以在它们之间通信的多个路由器。 传输侧适配器存储第一传送信息，并且根据第一传送信息控制要从第一内核接收的请求信号的传送。 接收侧适配器存储第二传送信息，并且根据第二传送信息控制要通过互连网络接收到第二核的请求信号的传送。 第一递送信息和第二递送信息被分层设置。

公开(公告)号：US08365021B2

公开(公告)日：2013-01-29

申请号：US11921742

申请日：2006-02-23

申请人： Hiroaki Inoue ,  Junji Sakai ,  Tsuyoshi Abe ,  Masaki Uekubo ,  Noriaki Suzuki ,  Masato Edahiro

发明人： Hiroaki Inoue ,  Junji Sakai ,  Tsuyoshi Abe ,  Masaki Uekubo ,  Noriaki Suzuki ,  Masato Edahiro

IPC分类号： G06F11/00 ,  G06F11/22

CPC分类号： G06F11/2028 ,  G06F9/4411 ,  G06F11/1482 ,  G06F11/1484 ,  G06F21/53 ,  G06F21/556 ,  G06F21/85 ,  G06F2221/2113

摘要： The information processing device which recovers a domain developing a fault caused by added application and device driver while maintaining security and reliability includes a plurality of processors, wherein the plurality of processors form a plurality of domains according to processing contents to be executed, and the processors in different domains communicate with each other through a communication unit, and which further includes a recovery unit for executing, for a domain developing a fault, failure recovery processing based on a failure recovery request notified by the domain and a recovery condition set in advance for each domain.

摘要翻译： 在维护安全性和可靠性的同时恢复由附加的应用和设备驱动程序引起的故障的域的信息处理设备包括多个处理器，其中，所述多个处理器根据要执行的处理内容形成多个域，并且处理器 在不同的域中通过通信单元相互通信，并且还包括恢复单元，用于针对发生故障的域执行基于所述域通知的故障恢复请求的故障恢复处理和预先设置的恢复条件 每个域。

公开(公告)号：US20100312815A1

公开(公告)日：2010-12-09

申请号：US12735707

申请日：2009-03-25

申请人： Masaki Uekubo

发明人： Masaki Uekubo

IPC分类号： G06F15/16

CPC分类号： G06F13/385

摘要： A data communications processor which mediates data sending and receiving in an embedded system is provided, wherein it avoids increase of processing due to accretion of number of communication data, disuses any resources for individual management of deadline for each data, and executes deadline management without a starvation. It does not execute receiving process successively for each communication datum; however, it executes receiving process for each assembled data accumulation partial area data as a whole for each prefixed period. In addition, a plurality of data accumulation partial areas in the data accumulating means 220, which is separated for each deadline, are executed batch receiving process respectively at the period according to the relative deadline time.

摘要翻译： 提供了一种在嵌入式系统中调停数据发送和接收的数据通信处理器，其中避免了由于增加通信数据的数量而导致的处理的增加，为每个数据的截止期间的个人管理而不利用任何资源， 饥饿。 对于每个通信数据不连续执行接收处理; 然而，对于每个组合的数据累积部分区域数据，对于每个前缀周期，整体执行接收处理。 此外，在每个截止时间分离的数据累积装置220中的多个数据累积部分区域分别在根据相对截止时间的时间段执行批量接收处理。

公开(公告)号：US20100183015A1

公开(公告)日：2010-07-22

申请号：US12663474

申请日：2008-05-30

申请人： Hiroaki Inoue ,  Masamichi Takagi ,  Masaki Uekubo ,  Sunao Torii ,  Masato Edahiro

发明人： Hiroaki Inoue ,  Masamichi Takagi ,  Masaki Uekubo ,  Sunao Torii ,  Masato Edahiro

IPC分类号： H04L12/56

CPC分类号： H04L63/0263 ,  G06F15/7825 ,  H04L63/0218

摘要： A semiconductor integrated circuit of the invention comprises a plurality of cores, and an interconnecting network including adaptors connected to each of the cores and a plurality of routers connecting the adaptors to communicate therebetween. Transmission side adaptors store first delivery information, and control delivery of the request signal to be received from the first core in accordance with the first delivery information. Reception side adaptors store second delivery information, and control delivery of the request signal to be received through the interconnecting network to the second core in accordance with the second delivery information. The first delivery information and the second delivery information are hierarchically set.

摘要翻译： 本发明的半导体集成电路包括多个核心，以及包括连接到每个核心的适配器的互连网络以及连接适配器以在它们之间通信的多个路由器。 传输侧适配器存储第一传送信息，并且根据第一传送信息控制要从第一内核接收的请求信号的传送。 接收侧适配器存储第二传送信息，并且根据第二传送信息控制要通过互连网络接收到第二核的请求信号的传送。 第一递送信息和第二递送信息被分层设置。

公开(公告)号：US20100172366A1

公开(公告)日：2010-07-08

申请号：US12663477

申请日：2008-05-30

申请人： Hiroaki Inoue ,  Masamichi Takagi ,  Masaki Uekubo ,  Sunao Torii ,  Masato Edahiro

发明人： Hiroaki Inoue ,  Masamichi Takagi ,  Masaki Uekubo ,  Sunao Torii ,  Masato Edahiro

IPC分类号： H04L12/56

CPC分类号： G06F15/16 ,  G06F21/50 ,  G06F21/577 ,  H04L29/06

摘要： A semiconductor integrated circuit of the invention comprises a plurality of cores, and an interconnecting network including adaptors connected to each of the cores and a plurality of routers connecting the adaptors to communicate therebetween. The adaptors keep delivery information indicating a delivery condition of a request signal received from the cores and control delivery of the request signal received from the cores in accordance with the delivery information.

摘要翻译： 本发明的半导体集成电路包括多个核心，以及包括连接到每个核心的适配器的互连网络以及连接适配器以在它们之间通信的多个路由器。 适配器保持指示从核心接收到的请求信号的传送条件的传送信息，并且根据传送信息控制从核心接收的请求信号的传送。

公开(公告)号：US06198657B1

公开(公告)日：2001-03-06

申请号：US09524560

申请日：2000-03-13

申请人： Masaki Uekubo ,  Shogo Miike

发明人： Masaki Uekubo ,  Shogo Miike

IPC分类号： G11C1607

CPC分类号： G11C16/22

摘要： A nonvolatile memory device is provided capable of shipping after setting it as a flash memory or as a one-time memory, and which cannot be altered to a flash memory once it has been used as a one-time memory. The nonvolatile memory device of the present invention has a circuit structure such that when a nonvolatile memory receives an instruction of prohibiting erasure of internal data, the instruction is stored by setting a prescribed flag provided in the nonvolatile memory at a predetermined value, and the content of the present nonvolatile memory cannot be erased after packaging, so that it is impossible for a user to alter the values of the flag which indicates whether erasure of data is prohibited or permitted.

摘要翻译： 提供一种非易失性存储装置，其在将其设置为闪存或一次性存储器之后能够运输，并且一旦将其用作一次性存储器就不能改变为闪存。 本发明的非易失性存储装置具有这样的电路结构，即当非易失性存储器接收到禁止内部数据的擦除的指令时，通过将设置在非易失性存储器中的规定标志设定为预定值来存储指令，并且内容 在包装之后不能擦除当前的非易失性存储器，因此用户不可能改变指示是否禁止或允许数据被擦除的标志的值。

公开(公告)号：US06191978B1

公开(公告)日：2001-02-20

申请号：US09553880

申请日：2000-04-20

申请人： Kazuo Watanabe ,  Masaki Uekubo

发明人： Kazuo Watanabe ,  Masaki Uekubo

IPC分类号： G11C1106

CPC分类号： G11C16/24 ,  G11C16/28 ,  G11C16/32

摘要： A non-volatile semiconductor memory device is provided which is capable of shortening time required for determining a reading voltage in its reading circuit and of improving a data reading speed. The non-volatile semiconductor memory device has a feedback-type bias circuit for letting currents to flow, in response to a first timing signal occurring when an address of a memory cell is selected from a load circuit to the memory cell to be connected to a bit line through a bit line decoder according to selection of the address and to be connected through a word line, causing a predetermined bias current to be supplied to the bit line and for letting a current to flow in accordance with an ON-state or OFF-state of the memory cell, causing a reading voltage to be produced at a connection point with the load circuit and a pre-charging circuit for letting currents to flow through the bit line in response to a second timing signal occurring in an early stage when the first timing signal is active and for interrupting currents flowing through the bit line in a last stage when the second timing signal is active.

摘要翻译： 提供了一种非易失性半导体存储器件，其能够缩短在其读取电路中确定读取电压所需的时间并提高数据读取速度。 非易失性半导体存储器件具有用于使电流流动的反馈型偏置电路，其响应于当将存储器单元的地址从负载电路选择为要连接到存储器单元的存储器单元时发生的第一定时信号 根据地址的选择通过位线解码器进行位线，并通过字线连接，使得预定的偏置电流被提供给位线，并使电流根据ON状态或OFF而流动 - 在存储单元的状态下，导致在与负载电路的连接点处产生读取电压，并且响应于在早期发生的第二定时信号而使电流流过位线的预充电电路， 当第二定时信号有效时，第一定时信号是有效的并且用于中断最后阶段中流过位线的电流。

公开(公告)号：US6163484A

公开(公告)日：2000-12-19

申请号：US299021

申请日：1999-04-26

申请人： Masaki Uekubo

发明人： Masaki Uekubo

IPC分类号： G11C16/06 ,  G11C16/28 ,  G11C16/34

CPC分类号： G11C16/3409 ,  G11C16/28 ,  G11C16/3404 ,  G11C16/3436 ,  G11C16/3445 ,  G11C16/3459

摘要： An electrically erasable and programmable non-volatile semiconductor storage device where data is read out by comparing the output of a memory cell and the output of a reference cell by a sense amplifier. In this device, the reference cell is built so that it has a given threshold voltage value, and the gate voltage of the memory cell and the gate voltage of the reference cell are allowed to be set independently.

摘要翻译： 一种电可擦除和可编程的非易失性半导体存储器件，其中通过读出放大器比较存储器单元的输出和参考单元的输出来读出数据。 在该器件中，构建参考单元以使其具有给定的阈值电压值，并允许单独设置存储单元的栅极电压和参考单元的栅极电压。