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    SEMICONDUCTOR INTEGRATED CIRCUIT AND FILTER CONTROL METHOD
    1.
    发明申请
    SEMICONDUCTOR INTEGRATED CIRCUIT AND FILTER CONTROL METHOD 有权
    半导体集成电路与滤波器控制方法

    公开(公告)号：US20100183015A1

    公开(公告)日：2010-07-22

    申请号：US12663474

    申请日：2008-05-30

    申请人： Hiroaki Inoue ,  Masamichi Takagi ,  Masaki Uekubo ,  Sunao Torii ,  Masato Edahiro

    发明人： Hiroaki Inoue ,  Masamichi Takagi ,  Masaki Uekubo ,  Sunao Torii ,  Masato Edahiro

    IPC分类号： H04L12/56

    CPC分类号： H04L63/0263 ,  G06F15/7825 ,  H04L63/0218

    摘要： A semiconductor integrated circuit of the invention comprises a plurality of cores, and an interconnecting network including adaptors connected to each of the cores and a plurality of routers connecting the adaptors to communicate therebetween. Transmission side adaptors store first delivery information, and control delivery of the request signal to be received from the first core in accordance with the first delivery information. Reception side adaptors store second delivery information, and control delivery of the request signal to be received through the interconnecting network to the second core in accordance with the second delivery information. The first delivery information and the second delivery information are hierarchically set.

    摘要翻译： 本发明的半导体集成电路包括多个核心，以及包括连接到每个核心的适配器的互连网络以及连接适配器以在它们之间通信的多个路由器。 传输侧适配器存储第一传送信息，并且根据第一传送信息控制要从第一内核接收的请求信号的传送。 接收侧适配器存储第二传送信息，并且根据第二传送信息控制要通过互连网络接收到第二核的请求信号的传送。 第一递送信息和第二递送信息被分层设置。

    SEMICONDUCTOR INTEGRATED CIRCUIT AND FILTER CONTROL METHOD
    2.
    发明申请
    SEMICONDUCTOR INTEGRATED CIRCUIT AND FILTER CONTROL METHOD 有权
    半导体集成电路和滤波器控制方法

    公开(公告)号：US20100172366A1

    公开(公告)日：2010-07-08

    申请号：US12663477

    申请日：2008-05-30

    申请人： Hiroaki Inoue ,  Masamichi Takagi ,  Masaki Uekubo ,  Sunao Torii ,  Masato Edahiro

    发明人： Hiroaki Inoue ,  Masamichi Takagi ,  Masaki Uekubo ,  Sunao Torii ,  Masato Edahiro

    IPC分类号： H04L12/56

    CPC分类号： G06F15/16 ,  G06F21/50 ,  G06F21/577 ,  H04L29/06

    摘要： A semiconductor integrated circuit of the invention comprises a plurality of cores, and an interconnecting network including adaptors connected to each of the cores and a plurality of routers connecting the adaptors to communicate therebetween. The adaptors keep delivery information indicating a delivery condition of a request signal received from the cores and control delivery of the request signal received from the cores in accordance with the delivery information.

    摘要翻译： 本发明的半导体集成电路包括多个核心，以及包括连接到每个核心的适配器的互连网络以及连接适配器以在它们之间通信的多个路由器。 适配器保持指示从核心接收到的请求信号的传送条件的传送信息，并且根据传送信息控制从核心接收的请求信号的传送。

    Semiconductor integrated circuit and filter control method
    3.
    发明授权
    Semiconductor integrated circuit and filter control method 有权
    半导体集成电路和滤波器控制方法

    公开(公告)号：US08531963B2

    公开(公告)日：2013-09-10

    申请号：US12663474

    申请日：2008-05-30

    申请人： Hiroaki Inoue ,  Masamichi Takagi ,  Masaki Uekubo ,  Sunao Torii ,  Masato Edahiro

    发明人： Hiroaki Inoue ,  Masamichi Takagi ,  Masaki Uekubo ,  Sunao Torii ,  Masato Edahiro

    IPC分类号： H04J3/14

    CPC分类号： H04L63/0263 ,  G06F15/7825 ,  H04L63/0218

    摘要： A semiconductor integrated circuit of the invention comprises a plurality of cores, and an interconnecting network including adaptors connected to each of the cores and a plurality of routers connecting the adaptors to communicate therebetween. Transmission side adaptors store first delivery information, and control delivery of the request signal to be received from the first core in accordance with the first delivery information. Reception side adaptors store second delivery information, and control delivery of the request signal to be received through the interconnecting network to the second core in accordance with the second delivery information. The first delivery information and the second delivery information are hierarchically set.

    摘要翻译： 本发明的半导体集成电路包括多个核心，以及包括连接到每个核心的适配器的互连网络以及连接适配器以在它们之间通信的多个路由器。 传输侧适配器存储第一传送信息，并且根据第一传送信息控制要从第一内核接收的请求信号的传送。 接收侧适配器存储第二传送信息，并且根据第二传送信息控制要通过互连网络接收到第二核的请求信号的传送。 第一递送信息和第二递送信息被分层设置。

    Information processing apparatus, execution environment transferring method and program thereof
    7.
    发明授权
    Information processing apparatus, execution environment transferring method and program thereof 有权
    信息处理装置，执行环境转移方法及程序

    公开(公告)号：US08473702B2

    公开(公告)日：2013-06-25

    申请号：US12602871

    申请日：2008-06-05

    申请人： Hiroaki Inoue ,  Tsuyoshi Abe ,  Junji Sakai ,  Masato Edahiro

    发明人： Hiroaki Inoue ,  Tsuyoshi Abe ,  Junji Sakai ,  Masato Edahiro

    IPC分类号： G06F12/00

    CPC分类号： G06F9/44505 ,  G06F9/4856

    摘要： Provided is an information processing device which enables transfer of an execution environment in a short time period without degrading basic performance of an execution environment and without requiring a large amount of memory.The information processing device comprises a basic side CPU 100 for executing basic processing and an addition side CPU 200 for executing additional processing, in which a transfer management unit 300 provided on the basic side CPU 100 transfers execution environment data 1000 including constitution information of an execution environment 30 of the additional processing to be executed on the addition side CPU and data in a memory corresponding to the execution environment to other information processing device and restores the execution environment to re-start the addition side CPU based on the received execution environment data 1000.

    摘要翻译： 提供一种能够在短时间内传送执行环境而不降低执行环境的基本性能而不需要大量存储器的信息处理装置。 信息处理装置包括用于执行基本处理的基本侧CPU 100和用于执行附加处理的附加侧CPU200，其中设置在基本侧CPU 100上的传送管理单元300传送包括执行的结构信息的执行环境数据1000 在附加侧CPU执行的附加处理的环境30和与执行环境相对应的存储器中的数据到其他信息处理装置，并且基于接收到的执行环境数据1000恢复执行环境以重新启动加法侧CPU 。

    MULTIPLE PROCESSOR SYSTEM, SYSTEM STRUCTURING METHOD IN MULTIPLE PROCESSOR SYSTEM AND PROGRAM THEREOF
    9.
    发明申请
    MULTIPLE PROCESSOR SYSTEM, SYSTEM STRUCTURING METHOD IN MULTIPLE PROCESSOR SYSTEM AND PROGRAM THEREOF 有权
    多处理器系统中的多处理器系统，系统结构方法及其程序

    公开(公告)号：US20100100706A1

    公开(公告)日：2010-04-22

    申请号：US12447513

    申请日：2007-11-01

    申请人： Hiroaki Inoue ,  Junji Sakai ,  Tsuyoshi Abe ,  Masato Edahiro

    发明人： Hiroaki Inoue ,  Junji Sakai ,  Tsuyoshi Abe ,  Masato Edahiro

    IPC分类号： G06F15/80

    CPC分类号： G06F9/5077 ,  G06F9/4405 ,  H04L29/08144 ,  H04L67/34

    摘要： For flexibly setting up an execution environment according to contents of processing to be executed while taking stability or a security level into consideration, the multiple processor system includes the execution environment main control unit 10 which determines CPU assignment at the time of deciding CPU assignment, the execution environment sub control unit 20 which controls starting, stopping and switching of an execution environment according to an instruction from the execution environment main control unit 10 to synchronize with the execution environment main control unit 10, and the execution environment management unit 30 which receives input of management information or reference refusal information of shared resources for each CPU 4 or each execution environment 100 to separate the execution environment main control unit 10 from the execution environment sub control units 20a through 20n, or the execution environment sub control units 20aA through 20n from each other.

    摘要翻译： 为了在考虑到稳定性或安全级别的同时根据要执行的处理的内容灵活地设置执行环境，多处理器系统包括确定CPU分配时的CPU分配的执行环境主控制单元10， 执行环境子控制单元20，其根据来自执行环境主控制单元10的指令控制执行环境的启动，停止和切换，以与执行环境主控制单元10同步;以及执行环境管理单元30，其接收输入 对于每个CPU 4或每个执行环境100的共享资源的管理信息或参考拒绝信息，以将执行环境主控制单元10与执行环境子控制单元20a至20n或执行环境子控制单元20aA至20n分离 彼此。

    Inter-processor communication system in parallel processing system by OS for single processors and program thereof
    10.
    发明申请
    Inter-processor communication system in parallel processing system by OS for single processors and program thereof 有权
    用于单处理器的OS并行处理系统中的处理器间通信系统及其程序

    公开(公告)号：US20050229184A1

    公开(公告)日：2005-10-13

    申请号：US11080730

    申请日：2005-03-16

    申请人： Hiroaki Inoue ,  Junji Sakai ,  Tsuyoshi Abe ,  Masato Edahiro

    发明人： Hiroaki Inoue ,  Junji Sakai ,  Tsuyoshi Abe ,  Masato Edahiro

    IPC分类号： G06F9/46 ,  G06F3/00 ,  G06F15/163

    CPC分类号： G06F9/544

    摘要： On a parallel processing system by an OS for single processors which operates, on a multiprocessor, an OS for single processors and an existing application to realize parallel processing by the multiprocessor with respect to the application, each processor includes a communication proxy unit which transfers data between tasks spreading over the processors by proxy and the communication proxy unit on a processor in which a task on a transmission side operates holds information about an address, on a processor, of a task on a reception side to receive data transferred from the task on the transmission side as proxy for the task on the reception side.

    摘要翻译： 在用于单处理器的操作系统的并行处理系统中，在多处理器上操作用于单个处理器的OS和现有应用以实现多处理器相对于应用的并行处理，每个处理器包括传送数据的通信代理单元 在处理器之间通过代理扩展的任务和处理器之间的通信代理单元，其中传输侧的任务在其上操作，在处理器上保存关于接收侧的任务的地址的信息，以接收从任务传送的数据 发送方作为接收方的任务的代理。