公开(公告)号：US20100183015A1

公开(公告)日：2010-07-22

申请号：US12663474

申请日：2008-05-30

申请人： Hiroaki Inoue ,  Masamichi Takagi ,  Masaki Uekubo ,  Sunao Torii ,  Masato Edahiro

发明人： Hiroaki Inoue ,  Masamichi Takagi ,  Masaki Uekubo ,  Sunao Torii ,  Masato Edahiro

IPC分类号： H04L12/56

CPC分类号： H04L63/0263 ,  G06F15/7825 ,  H04L63/0218

摘要： A semiconductor integrated circuit of the invention comprises a plurality of cores, and an interconnecting network including adaptors connected to each of the cores and a plurality of routers connecting the adaptors to communicate therebetween. Transmission side adaptors store first delivery information, and control delivery of the request signal to be received from the first core in accordance with the first delivery information. Reception side adaptors store second delivery information, and control delivery of the request signal to be received through the interconnecting network to the second core in accordance with the second delivery information. The first delivery information and the second delivery information are hierarchically set.

摘要翻译： 本发明的半导体集成电路包括多个核心，以及包括连接到每个核心的适配器的互连网络以及连接适配器以在它们之间通信的多个路由器。 传输侧适配器存储第一传送信息，并且根据第一传送信息控制要从第一内核接收的请求信号的传送。 接收侧适配器存储第二传送信息，并且根据第二传送信息控制要通过互连网络接收到第二核的请求信号的传送。 第一递送信息和第二递送信息被分层设置。

公开(公告)号：US20100172366A1

公开(公告)日：2010-07-08

申请号：US12663477

申请日：2008-05-30

申请人： Hiroaki Inoue ,  Masamichi Takagi ,  Masaki Uekubo ,  Sunao Torii ,  Masato Edahiro

发明人： Hiroaki Inoue ,  Masamichi Takagi ,  Masaki Uekubo ,  Sunao Torii ,  Masato Edahiro

IPC分类号： H04L12/56

CPC分类号： G06F15/16 ,  G06F21/50 ,  G06F21/577 ,  H04L29/06

摘要： A semiconductor integrated circuit of the invention comprises a plurality of cores, and an interconnecting network including adaptors connected to each of the cores and a plurality of routers connecting the adaptors to communicate therebetween. The adaptors keep delivery information indicating a delivery condition of a request signal received from the cores and control delivery of the request signal received from the cores in accordance with the delivery information.

摘要翻译： 本发明的半导体集成电路包括多个核心，以及包括连接到每个核心的适配器的互连网络以及连接适配器以在它们之间通信的多个路由器。 适配器保持指示从核心接收到的请求信号的传送条件的传送信息，并且根据传送信息控制从核心接收的请求信号的传送。

公开(公告)号：US20100100706A1

公开(公告)日：2010-04-22

申请号：US12447513

申请日：2007-11-01

申请人： Hiroaki Inoue ,  Junji Sakai ,  Tsuyoshi Abe ,  Masato Edahiro

发明人： Hiroaki Inoue ,  Junji Sakai ,  Tsuyoshi Abe ,  Masato Edahiro

IPC分类号： G06F15/80

CPC分类号： G06F9/5077 ,  G06F9/4405 ,  H04L29/08144 ,  H04L67/34

摘要： For flexibly setting up an execution environment according to contents of processing to be executed while taking stability or a security level into consideration, the multiple processor system includes the execution environment main control unit 10 which determines CPU assignment at the time of deciding CPU assignment, the execution environment sub control unit 20 which controls starting, stopping and switching of an execution environment according to an instruction from the execution environment main control unit 10 to synchronize with the execution environment main control unit 10, and the execution environment management unit 30 which receives input of management information or reference refusal information of shared resources for each CPU 4 or each execution environment 100 to separate the execution environment main control unit 10 from the execution environment sub control units 20a through 20n, or the execution environment sub control units 20aA through 20n from each other.

摘要翻译： 为了在考虑到稳定性或安全级别的同时根据要执行的处理的内容灵活地设置执行环境，多处理器系统包括确定CPU分配时的CPU分配的执行环境主控制单元10， 执行环境子控制单元20，其根据来自执行环境主控制单元10的指令控制执行环境的启动，停止和切换，以与执行环境主控制单元10同步;以及执行环境管理单元30，其接收输入 对于每个CPU 4或每个执行环境100的共享资源的管理信息或参考拒绝信息，以将执行环境主控制单元10与执行环境子控制单元20a至20n或执行环境子控制单元20aA至20n分离 彼此。

公开(公告)号：US20050229184A1

公开(公告)日：2005-10-13

申请号：US11080730

申请日：2005-03-16

申请人： Hiroaki Inoue ,  Junji Sakai ,  Tsuyoshi Abe ,  Masato Edahiro

发明人： Hiroaki Inoue ,  Junji Sakai ,  Tsuyoshi Abe ,  Masato Edahiro

IPC分类号： G06F9/46 ,  G06F3/00 ,  G06F15/163

CPC分类号： G06F9/544

摘要： On a parallel processing system by an OS for single processors which operates, on a multiprocessor, an OS for single processors and an existing application to realize parallel processing by the multiprocessor with respect to the application, each processor includes a communication proxy unit which transfers data between tasks spreading over the processors by proxy and the communication proxy unit on a processor in which a task on a transmission side operates holds information about an address, on a processor, of a task on a reception side to receive data transferred from the task on the transmission side as proxy for the task on the reception side.

摘要翻译： 在用于单处理器的操作系统的并行处理系统中，在多处理器上操作用于单个处理器的OS和现有应用以实现多处理器相对于应用的并行处理，每个处理器包括传送数据的通信代理单元 在处理器之间通过代理扩展的任务和处理器之间的通信代理单元，其中传输侧的任务在其上操作，在处理器上保存关于接收侧的任务的地址的信息，以接收从任务传送的数据 发送方作为接收方的任务的代理。

公开(公告)号：US5944836A

公开(公告)日：1999-08-31

申请号：US822464

申请日：1997-03-21

申请人： Masato Edahiro

发明人： Masato Edahiro

IPC分类号： G06F1/10 ,  G06F17/50 ,  H01L21/82 ,  H01L21/822 ,  H01L27/04 ,  H04L7/00

CPC分类号： G06F1/10

摘要： The invention provides a clock signal distributing circuit wherein the position at which the buffer section is disposed is determined from the positions and characteristics of the clock signal input section and the load section and the characteristics of the buffer section and the wiring section, and wirings are made through the clock signal input section, one or more stage buffer sections, and the load section, so that the signal transmission delay time as well as the skew of clock signals can be adjusted.

摘要翻译： 本发明提供一种时钟信号分配电路，其中根据时钟信号输入部分和负载部分的位置和特性以及缓冲部分和布线部分的特性确定缓冲部分的位置，并且布线是 通过时钟信号输入部分，一个或多个级缓冲器部分和负载部分，从而可以调整信号传输延迟时间以及时钟信号的偏斜。

公开(公告)号：US20160018794A1

公开(公告)日：2016-01-21

申请号：US14768635

申请日：2014-02-12

申请人： Kota SATA ,  Junichi KAKO ,  Satoru WATANABE ,  Yuta SUZUKI ,  Masato EDAHIRO

发明人： Kota SATA ,  Junichi KAKO ,  Satoru WATANABE ,  Yuta SUZUKI ,  Masato EDAHIRO

IPC分类号： G05B11/42

摘要： A control device according to the present invention includes a plurality of arithmetic units that operate in parallel. A sensor value of the control amount is input to the first arithmetic unit in a signal transmission sequence, and a correction amount for the manipulation amount is output from the last arithmetic unit in the signal transmission sequence. The first arithmetic unit has a controller that produces an output by processing the input sensor value, and the arithmetic units other than the first arithmetic unit has a delay element that delays an input by a predetermined number of steps and a controller that produces an output by processing the delayed input.

摘要翻译： 根据本发明的控制装置包括并行操作的多个运算单元。 控制量的传感器值以信号发送顺序输入到第一算术单元，并且在信号发送序列中从最后运算单元输出用于操作量的校正量。 第一算术单元具有通过处理输入传感器值产生输出的控制器，除第一算术单元之外的算术单元具有将输入延迟预定步数的延迟元件和产生输出的控制器 处理延迟输入。

公开(公告)号：US08473702B2

公开(公告)日：2013-06-25

申请号：US12602871

申请日：2008-06-05

申请人： Hiroaki Inoue ,  Tsuyoshi Abe ,  Junji Sakai ,  Masato Edahiro

发明人： Hiroaki Inoue ,  Tsuyoshi Abe ,  Junji Sakai ,  Masato Edahiro

IPC分类号： G06F12/00

CPC分类号： G06F9/44505 ,  G06F9/4856

摘要： Provided is an information processing device which enables transfer of an execution environment in a short time period without degrading basic performance of an execution environment and without requiring a large amount of memory.The information processing device comprises a basic side CPU 100 for executing basic processing and an addition side CPU 200 for executing additional processing, in which a transfer management unit 300 provided on the basic side CPU 100 transfers execution environment data 1000 including constitution information of an execution environment 30 of the additional processing to be executed on the addition side CPU and data in a memory corresponding to the execution environment to other information processing device and restores the execution environment to re-start the addition side CPU based on the received execution environment data 1000.

摘要翻译： 提供一种能够在短时间内传送执行环境而不降低执行环境的基本性能而不需要大量存储器的信息处理装置。 信息处理装置包括用于执行基本处理的基本侧CPU 100和用于执行附加处理的附加侧CPU200，其中设置在基本侧CPU 100上的传送管理单元300传送包括执行的结构信息的执行环境数据1000 在附加侧CPU执行的附加处理的环境30和与执行环境相对应的存储器中的数据到其他信息处理装置，并且基于接收到的执行环境数据1000恢复执行环境以重新启动加法侧CPU 。

公开(公告)号：US07418703B2

公开(公告)日：2008-08-26

申请号：US10390595

申请日：2003-03-19

申请人： Masato Edahiro ,  Yoshiyuki Ito ,  Junji Sakai ,  Tetsuya Minakami ,  Hiroaki Inoue

发明人： Masato Edahiro ,  Yoshiyuki Ito ,  Junji Sakai ,  Tetsuya Minakami ,  Hiroaki Inoue

IPC分类号： G06F9/46

CPC分类号： G06F9/5066

摘要： The present invention relates to a parallel processing system by an OS for single processor capable of operating an OS for single processor and an existing application on a multiprocessor and achieving parallel processing by a multiprocessor with respect to the application, wherein the multiprocessor are logically divided into two groups, i.e., a first processor side and a second processor side, and units of work that are parallelizable within the application operating on the processors on the first processor side are controlled as new units of work on the processors on the second processor side.

公开(公告)号：US20150378335A1

公开(公告)日：2015-12-31

申请号：US14768606

申请日：2014-02-12

申请人： Kota SATA ,  Junichi KAKO ,  Satoru WATANABE ,  Yuta SUZUKI ,  Masato EDAHIRO

发明人： Kota SATA ,  Junichi KAKO ,  Satoru WATANABE ,  Yuta SUZUKI ,  Masato EDAHIRO

IPC分类号： G05B17/02

CPC分类号： G05B17/02

摘要： The present invention relates to a control device design method for a control device that determines a manipulation amount of a control object having a dead time by feedback control so as to bring a control amount of the control object closer to a target value. The method according to the present invention includes a step of designing a feedback loop that computes a correction amount for the manipulation amount using a plurality of controllers including a prediction model of the control object, a step of deriving the same number of delay elements as the plurality of controllers from a dead time element of the prediction model, and a step of allocating the plurality of controllers associated with the delay elements to a plurality of arithmetic units so that the computation of the feedback loop is performed by parallel computation by the plurality of arithmetic units that operate in parallel.

摘要翻译： 本发明涉及一种控制装置的控制装置设计方法，其通过反馈控制确定具有死区时间的控制对象的操作量，以使控制对象的控制量更接近目标值。 根据本发明的方法包括以下步骤：使用包括控制对象的预测模型的多个控制器来计算操作量的校正量的反馈回路的步骤，导出与所述控制对象相同数量的延迟元件的步骤 来自预测模型的死区时间元素的多个控制器，以及将与延迟元件相关联的多个控制器分配给多个算术单元的步骤，使得反馈回路的计算由多个 并行运算的算术单元。

公开(公告)号：US08887165B2

公开(公告)日：2014-11-11

申请号：US13579865

申请日：2011-02-02

申请人： Noriaki Suzuki ,  Masato Edahiro ,  Junji Sakai

发明人： Noriaki Suzuki ,  Masato Edahiro ,  Junji Sakai

IPC分类号： G06F9/46 ,  G06F9/48

CPC分类号： G06F9/4887 ,  G06F2209/483

摘要： Disclosed is an automatic optimization system capable of searching for an allocation with a good performance from among a plurality of task allocations which can be scheduled in a system of a development target configured with a plurality of periodic tasks. A task allocation optimization system for a multi-core processor including a plurality of cores calculates a response time of each of a plurality of tasks which are core allocation decision targets, and outputs an accumulative value of the calculated response time as an evaluation function value which is an index representing excellence of a task allocation. A task allocation from which a good evaluation function value is calculated is searched based on the evaluation function value. A candidate having a good evaluation function value among a plurality of searched task allocation candidates is held.

摘要翻译： 公开了能够从配置有多个周期性任务的开发目标的系统中调度的多个任务分配中搜索具有良好性能的分配的自动优化系统。 包括多个核的多核处理器的任务分配优化系统计算作为核心分配决定目标的多个任务中的每一个的响应时间，并将所计算的响应时间的累积值作为评估函数值输出， 是表示任务分配卓越的索引。 根据评价函数值搜索计算好评价函数值的任务分配。 保持在多个搜索到的任务分配候选中具有良好评价函数值的候选者。