公开(公告)号：US20100183015A1

公开(公告)日：2010-07-22

申请号：US12663474

申请日：2008-05-30

申请人： Hiroaki Inoue ,  Masamichi Takagi ,  Masaki Uekubo ,  Sunao Torii ,  Masato Edahiro

发明人： Hiroaki Inoue ,  Masamichi Takagi ,  Masaki Uekubo ,  Sunao Torii ,  Masato Edahiro

IPC分类号： H04L12/56

CPC分类号： H04L63/0263 ,  G06F15/7825 ,  H04L63/0218

摘要： A semiconductor integrated circuit of the invention comprises a plurality of cores, and an interconnecting network including adaptors connected to each of the cores and a plurality of routers connecting the adaptors to communicate therebetween. Transmission side adaptors store first delivery information, and control delivery of the request signal to be received from the first core in accordance with the first delivery information. Reception side adaptors store second delivery information, and control delivery of the request signal to be received through the interconnecting network to the second core in accordance with the second delivery information. The first delivery information and the second delivery information are hierarchically set.

摘要翻译： 本发明的半导体集成电路包括多个核心，以及包括连接到每个核心的适配器的互连网络以及连接适配器以在它们之间通信的多个路由器。 传输侧适配器存储第一传送信息，并且根据第一传送信息控制要从第一内核接收的请求信号的传送。 接收侧适配器存储第二传送信息，并且根据第二传送信息控制要通过互连网络接收到第二核的请求信号的传送。 第一递送信息和第二递送信息被分层设置。

公开(公告)号：US20100172366A1

公开(公告)日：2010-07-08

申请号：US12663477

申请日：2008-05-30

申请人： Hiroaki Inoue ,  Masamichi Takagi ,  Masaki Uekubo ,  Sunao Torii ,  Masato Edahiro

发明人： Hiroaki Inoue ,  Masamichi Takagi ,  Masaki Uekubo ,  Sunao Torii ,  Masato Edahiro

IPC分类号： H04L12/56

CPC分类号： G06F15/16 ,  G06F21/50 ,  G06F21/577 ,  H04L29/06

摘要： A semiconductor integrated circuit of the invention comprises a plurality of cores, and an interconnecting network including adaptors connected to each of the cores and a plurality of routers connecting the adaptors to communicate therebetween. The adaptors keep delivery information indicating a delivery condition of a request signal received from the cores and control delivery of the request signal received from the cores in accordance with the delivery information.

摘要翻译： 本发明的半导体集成电路包括多个核心，以及包括连接到每个核心的适配器的互连网络以及连接适配器以在它们之间通信的多个路由器。 适配器保持指示从核心接收到的请求信号的传送条件的传送信息，并且根据传送信息控制从核心接收的请求信号的传送。

公开(公告)号：US08531963B2

公开(公告)日：2013-09-10

申请号：US12663474

申请日：2008-05-30

申请人： Hiroaki Inoue ,  Masamichi Takagi ,  Masaki Uekubo ,  Sunao Torii ,  Masato Edahiro

发明人： Hiroaki Inoue ,  Masamichi Takagi ,  Masaki Uekubo ,  Sunao Torii ,  Masato Edahiro

IPC分类号： H04J3/14

CPC分类号： H04L63/0263 ,  G06F15/7825 ,  H04L63/0218

摘要： A semiconductor integrated circuit of the invention comprises a plurality of cores, and an interconnecting network including adaptors connected to each of the cores and a plurality of routers connecting the adaptors to communicate therebetween. Transmission side adaptors store first delivery information, and control delivery of the request signal to be received from the first core in accordance with the first delivery information. Reception side adaptors store second delivery information, and control delivery of the request signal to be received through the interconnecting network to the second core in accordance with the second delivery information. The first delivery information and the second delivery information are hierarchically set.

摘要翻译： 本发明的半导体集成电路包括多个核心，以及包括连接到每个核心的适配器的互连网络以及连接适配器以在它们之间通信的多个路由器。 传输侧适配器存储第一传送信息，并且根据第一传送信息控制要从第一内核接收的请求信号的传送。 接收侧适配器存储第二传送信息，并且根据第二传送信息控制要通过互连网络接收到第二核的请求信号的传送。 第一递送信息和第二递送信息被分层设置。

公开(公告)号：US08412867B2

公开(公告)日：2013-04-02

申请号：US12663477

申请日：2008-05-30

申请人： Hiroaki Inoue ,  Masamichi Takagi ,  Masaki Uekubo ,  Sunao Torii ,  Masato Edahiro

发明人： Hiroaki Inoue ,  Masamichi Takagi ,  Masaki Uekubo ,  Sunao Torii ,  Masato Edahiro

IPC分类号： G06F13/12 ,  H04L12/56

CPC分类号： G06F15/16 ,  G06F21/50 ,  G06F21/577 ,  H04L29/06

摘要： A semiconductor integrated circuit of the invention comprises a plurality of cores, and an interconnecting network including adaptors connected to each of the cores and a plurality of routers connecting the adaptors to communicate therebetween. The adaptors keep delivery information indicating a delivery condition of a request signal received from the cores and control delivery of the request signal received from the cores in accordance with the delivery information.

摘要翻译： 本发明的半导体集成电路包括多个核心，以及包括连接到每个核心的适配器的互连网络以及连接适配器以在它们之间通信的多个路由器。 适配器保持指示从核心接收到的请求信号的传送条件的传送信息，并且根据传送信息控制从核心接收的请求信号的传送。

公开(公告)号：US20110026405A1

公开(公告)日：2011-02-03

申请号：US12935035

申请日：2009-04-30

申请人： Masamichi Takagi ,  Sunao Torii

发明人： Masamichi Takagi ,  Sunao Torii

IPC分类号： H04L12/56 ,  H04L12/26

CPC分类号： H04L45/00 ,  H04L45/60 ,  H04L49/109 ,  H04L49/1546 ,  H04L49/251

摘要： A router includes: a flit arrival time management section that records flit arrival time which is the time at which the packet is received for the first time, transmission interval of the packet which are acquired from a control packet transmitted prior to the first transmission of a packet and input and output channels of the control packet and requires a crossbar section for an output channel from which the packet is supposed to be output before the flit arrival time; a switch assignment section that performs arbitration on the output channel request and performs input/output connection relationship setting processing; and a switch assignment verification section that verifies whether a result of the input/output connection relationship setting processing coincides with the actual routing of the packet. The cross bar section performs switching of the arriving packet using a result of the input/output connection relationship processing.

摘要翻译： 路由器包括：飞行到达时间管理部，其记录作为第一次接收分组的时间的飞行到达时间，从在第一次发送之前发送的控制分组获取的分组的发送间隔 分组和控制分组的输入和输出通道，并且需要用于输出通道的横截面部分，在该输出通道之前，应该在该飞行器到达时间之前输出该分组; 开关分配单元，对所述输出通道请求进行仲裁，并进行输入/输出连接关系设定处理; 以及开关分配验证部，其验证输入/输出连接关系设置处理的结果是否与分组的实际路由一致。 横杆部分使用输入/输出连接关系处理的结果来执行到达的分组的切换。

公开(公告)号：US08638665B2

公开(公告)日：2014-01-28

申请号：US12935035

申请日：2009-04-30

申请人： Masamichi Takagi ,  Sunao Torii

发明人： Masamichi Takagi ,  Sunao Torii

IPC分类号： G06F11/00

CPC分类号： H04L45/00 ,  H04L45/60 ,  H04L49/109 ,  H04L49/1546 ,  H04L49/251

摘要： A router includes: a flit arrival time management section that records flit arrival time which is the time at which the packet is received for the first time, transmission interval of the packet which are acquired from a control packet transmitted prior to the first transmission of a packet and input and output channels of the control packet and requires a crossbar section for an output channel from which the packet is supposed to be output before the flit arrival time; a switch assignment section that performs arbitration on the output channel request and performs input/output connection relationship setting processing; and a switch assignment verification section that verifies whether a result of the input/output connection relationship setting processing coincides with the actual routing of the packet. The cross bar section performs switching of the arriving packet using a result of the input/output connection relationship processing.

摘要翻译： 路由器包括：飞行到达时间管理部，其记录作为第一次接收分组的时间的飞行到达时间，从在第一次发送之前发送的控制分组获取的分组的发送间隔 分组和控制分组的输入和输出通道，并且需要用于输出通道的横截面部分，在该输出通道之前，应该在该飞行器到达时间之前输出该分组; 开关分配单元，对所述输出通道请求进行仲裁，并进行输入/输出连接关系设定处理; 以及开关分配验证部，其验证输入/输出连接关系设置处理的结果是否与分组的实际路由一致。 横杆部分使用输入/输出连接关系处理的结果来执行到达的分组的切换。

公开(公告)号：US20100100886A1

公开(公告)日：2010-04-22

申请号：US12529367

申请日：2008-02-05

申请人： Masamichi Takagi ,  Masayuki Mizuno ,  Hiroaki Inoue

发明人： Masamichi Takagi ,  Masayuki Mizuno ,  Hiroaki Inoue

IPC分类号： G06F9/50

CPC分类号： G06F9/5027 ,  G06F11/1428 ,  G06F11/3419 ,  G06F11/3433 ,  G06F2209/483 ,  G06F2209/501

摘要： Even if a multiprocessor includes an uneven performance core, an inoperative core or a core that does not satisfy such a performance as designed but if the contrivance of task allocation can satisfy the requirement of an application to be executed, the multiple processors are shipped. In a task group allocation method for allocating, to a processor having a plurality of cores, task groups included in an application for the processor to execute, a calculation section measures performances and disposition patterns of the cores, generates a restricting condition associating the measured performances and disposition patterns of the cores with information indicating whether the application can be executed, and, with reference to the restricting condition, reallocates to the cores, the task groups that have previously been allocated to the cores.

摘要翻译： 即使多处理器包括不均衡的性能核心，不能满足设计性能的不工作核心或核心，但如果任务分配的设计能够满足执行应用程序的要求，则会发送多个处理器。 在用于将具有多个核心的处理器分配给应用程序中的处理器执行的任务组的任务组分配方法中，计算部分测量核心的性能和配置模式，产生将测量性能 以及具有指示是否可以执行应用的信息的核心的配置模式，并且参考限制条件将已经分配给核心的任务组重新分配给核心。

公开(公告)号：US08140912B2

公开(公告)日：2012-03-20

申请号：US12447512

申请日：2007-10-19

申请人： Hiroaki Inoue ,  Masamichi Takagi ,  Masayuki Mizuno

发明人： Hiroaki Inoue ,  Masamichi Takagi ,  Masayuki Mizuno

IPC分类号： G06F11/00

CPC分类号： G06F11/0721 ,  G06F11/0751 ,  G06F11/2236

摘要： A semiconductor integrated circuit comprising a processor having an output signal of instruction log information and being operable in a program in memory is disclosed. The semiconductor integrated circuit comprises trace determination circuit for comparing an instruction code that corresponds to the instruction log information from a processor with an instruction code that is read from the memory to detect faults.

摘要翻译： 公开了一种半导体集成电路，其包括具有指令日志信息的输出信号并且可在存储器中的程序中操作的处理器。 半导体集成电路包括跟踪确定电路，用于将来自处理器的与指令日志信息相对应的指令代码与从存储器读取的指令代码进行比较以检测故障。

公开(公告)号：US08108719B2

公开(公告)日：2012-01-31

申请号：US12441289

申请日：2007-09-13

申请人： Hiroaki Inoue ,  Masamichi Takagi ,  Masayuki Mizuno

发明人： Hiroaki Inoue ,  Masamichi Takagi ,  Masayuki Mizuno

IPC分类号： G06F11/00

CPC分类号： G06F11/2043 ,  G06F11/2023 ,  G06F11/2025 ,  G06F11/203 ,  G06F11/2033 ,  G06F11/2035

摘要： An information processing device comprises a plurality of processing units on which OSs and execution environments operate, and shared peripheral devices shared by the plurality of processing units. The information processing device is provided with a failure concealing device for concealing a failure which has occurred in a processing unit. The failure concealing device determines a substitutional processing unit that will act as a substitute for a failed processing unit so that the OS and execution environment which have operated on the failed processing unit will operate on the substitutional processing unit, switches the OS and execution environment which have operated on the failed processing unit so that they will operate on the substitutional processing unit, and switches a shared resource used by the failed processing unit such that it is available to the substitutional processing unit.

摘要翻译： 信息处理装置包括操作系统和执行环境操作的多个处理单元以及由多个处理单元共享的共享外围设备。 信息处理装置设置有用于隐藏处理单元中发生的故障的故障隐藏装置。 故障隐藏装置决定将作为故障处理单元的替代物的替代处理单元，使得在故障处理单元上操作的OS和执行环境将在替代处理单元上操作，切换OS和执行环境， 在故障处理单元上操作，使得它们在替代处理单元上操作，并且切换由故障处理单元使用的共享资源，使得它可用于替代处理单元。

公开(公告)号：US20100077259A1

公开(公告)日：2010-03-25

申请号：US12447524

申请日：2007-10-17

申请人： Hiroaki Inoue ,  Masamichi Takagi ,  Masayuki Mizuno

发明人： Hiroaki Inoue ,  Masamichi Takagi ,  Masayuki Mizuno

IPC分类号： G06F9/30 ,  G06F11/07

CPC分类号： G06F11/277

摘要： An apparatus for performing a screening test of a semiconductor integrated circuit is disclosed, the semiconductor integrated circuit comprising a plurality of processors each having an output signal for instruction execution information, and the processors being programmatically operable. The apparatus for performing a screening test of a semiconductor integrated circuit comprises: an instruction/data signal synchronization circuit for synchronizing the supplying of instructions to said respective processors and for synchronizing the supplying of data to said respective processors; and a trace comparison circuit for comparing instruction execution information that are output from the respective processors to determine whether or not any of said processors has output different instruction execution information.

摘要翻译： 公开了一种用于执行半导体集成电路的屏蔽测试的装置，所述半导体集成电路包括多个处理器，每个处理器具有用于指令执行信息的输出信号，并且所述处理器可编程地可操作。 用于执行半导体集成电路的屏蔽测试的装置包括：指令/数据信号同步电路，用于将指令的提供同步到所述各个处理器并用于同步向所述各个处理器提供数据; 以及跟踪比较电路，用于比较从各个处理器输出的指令执行信息，以确定所述处理器中的任何一个是否输出了不同的指令执行信息。