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公开(公告)号：US20130062747A1
公开(公告)日：2013-03-14
申请号：US13613031
申请日：2012-09-13
申请人： TOSHIHIKO AKIBA , Minoru Kimura , Masao Odagiri
发明人： TOSHIHIKO AKIBA , Minoru Kimura , Masao Odagiri
IPC分类号： H01L23/495
CPC分类号： H01L21/78 , B28D5/022 , H01L23/3121 , H01L24/48 , H01L24/49 , H01L2224/05554 , H01L2224/48095 , H01L2224/48247 , H01L2224/48465 , H01L2224/49171 , H01L2924/00014 , H01L2924/01013 , H01L2924/01019 , H01L2924/01029 , H01L2924/01078 , H01L2924/01079 , H01L2924/10156 , H01L2924/10157 , H01L2924/10253 , H01L2924/14 , H01L2924/181 , H01L2924/00 , H01L2924/00012 , H01L2224/45099 , H01L2224/45015 , H01L2924/207
摘要： In a manufacturing method of a semiconductor device having a multilevel interconnect layer including a low-k layer, a two-step cutting technique is used for dicing. After formation of a groove in a semiconductor wafer with a tapered blade, the groove is divided with a straight blade thinner than the groove width. The multilevel interconnect layer portion is cut while being covered with a tapered face and then the wafer is separated with a thin blade which is not brought into contact with the multilevel interconnect layer portion. The wafer can thus be diced without damaging a relatively fragile low-k layer.
摘要翻译： 在具有包括低k层的多层互连层的半导体器件的制造方法中，使用两步切割技术进行切割。 在具有锥形刀片的半导体晶片中形成凹槽之后，将沟槽分割成比凹槽宽度更薄的直线刀片。 多层互连层部分被切割，同时被锥形面覆盖，然后用不与多层互连层部分接触的薄片分离晶片。 因此，可以切割晶片而不破坏相对脆弱的低k层。
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公开(公告)号：US08298963B2
公开(公告)日：2012-10-30
申请号：US12690733
申请日：2010-01-20
申请人： Toshihiko Akiba , Minoru Kimura , Masao Odagiri
发明人： Toshihiko Akiba , Minoru Kimura , Masao Odagiri
IPC分类号： H01L23/522
CPC分类号： H01L21/78 , B28D5/022 , H01L23/3121 , H01L24/48 , H01L24/49 , H01L2224/05554 , H01L2224/48095 , H01L2224/48247 , H01L2224/48465 , H01L2224/49171 , H01L2924/00014 , H01L2924/01013 , H01L2924/01019 , H01L2924/01029 , H01L2924/01078 , H01L2924/01079 , H01L2924/10156 , H01L2924/10157 , H01L2924/10253 , H01L2924/14 , H01L2924/181 , H01L2924/00 , H01L2924/00012 , H01L2224/45099 , H01L2224/45015 , H01L2924/207
摘要： With a recent shrinking semiconductor process, insulating layers formed between interconnect layers are becoming thin. To avoid parasitic capacitance between them, materials of a low dielectric constant have been used for an insulating layer in a multilevel interconnect. Low-k materials, however, have low strength compared with the conventional insulating layers. Porous low-k materials are structurally fragile. The invention therefore provides a manufacturing method of a semiconductor device having a multilevel interconnect layer including a low-k layer. According to the method, in a two-step cutting system dicing in which after formation of a groove in a semiconductor water with a tapered blade, the groove is divided with a straight blade thinner than the groove width, the multilevel interconnect layer portion is cut while being covered with a tapered face and then the wafer is separated with a thin blade which is not brought into contact with the multilevel interconnect layer portion. The wafer can be diced without damaging a relatively fragile low-k layer.
摘要翻译： 随着半导体工艺的缩小，互连层之间形成的绝缘层变薄。 为了避免它们之间的寄生电容，低介电常数的材料已被用于多层互连中的绝缘层。 然而，与常规绝缘层相比，低k材料具有低强度。 多孔低k材料结构脆弱。 因此，本发明提供了具有包括低k层的多层互连层的半导体器件的制造方法。 根据该方法，在具有锥形叶片的半导体水中形成槽之后的两步切割系统切割中，将沟槽分割成比槽宽度薄的直线片，切割多层互连层部分 同时用锥形表面覆盖，然后用不与多层互连层部分接触的薄片分离晶片。 可以切割晶片，而不会损坏相对脆弱的低k层。
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公开(公告)号：US20080286948A1
公开(公告)日：2008-11-20
申请号：US12170020
申请日：2008-07-09
申请人： Chuichi Miyazaki , Yoshiyuki Abe , Toshihide Uematsu , Minoru Kimura , Kazunari Suzuki , Masao Odagiri , Hideyuki Suga , Manabu Takata
发明人： Chuichi Miyazaki , Yoshiyuki Abe , Toshihide Uematsu , Minoru Kimura , Kazunari Suzuki , Masao Odagiri , Hideyuki Suga , Manabu Takata
IPC分类号： H01L21/00
CPC分类号： H01L21/6835 , H01L21/02238 , H01L21/02255 , H01L21/30625 , H01L21/314 , H01L21/31654 , H01L21/31675 , H01L21/6836 , H01L21/78 , H01L2221/68327 , H01L2221/6834
摘要： A technique capable of stably releasing chips from a dicing tape, includes grinding a back surface of a semiconductor wafer, while adhering a pressure sensitive adhesive tape to a circuit forming surface of the semiconductor wafer formed with an integrated circuit, to achieve a predetermined thickness and forcibly oxidizing the back surface of the semiconductor wafer. Then, the pressure sensitive adhesive tape adhered to the circuit forming surface of the semiconductor wafer is released, and a dicing tape is adhered to the back surface of the semiconductor wafer. Further, the semiconductor wafer is divided by dicing it into individual chips, and then the back surface of the chip is pressed by way of the dicing tape, thereby releasing the chips from the dicing tape.
摘要翻译： 一种能够从切割带稳定地释放芯片的技术包括：将压敏粘合带粘附到形成有集成电路的半导体晶片的电路形成表面上，研磨半导体晶片的背面，以实现预定厚度， 强制氧化半导体晶片的背面。 然后，剥离粘附到半导体晶片的电路形成表面的压敏粘合带，并将切割带粘附到半导体晶片的背面。 此外，通过将半导体晶片切割成单独的芯片来分割半导体晶片，然后通过切割带对芯片的背面进行压制，从而从切割带释放芯片。
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公开(公告)号：US20050142815A1
公开(公告)日：2005-06-30
申请号：US11020049
申请日：2004-12-23
申请人： Chuichi Miyazaki , Yoshiyuki Abe , Toshihide Uematsu , Minoru Kimura , Kazunari Suzuki , Masao Odagiri , Hideyuki Suga , Manabu Takata
发明人： Chuichi Miyazaki , Yoshiyuki Abe , Toshihide Uematsu , Minoru Kimura , Kazunari Suzuki , Masao Odagiri , Hideyuki Suga , Manabu Takata
IPC分类号： H01L21/301 , H01L21/304 , H01L21/306 , H01L21/314 , H01L21/316 , H01L21/46 , H01L21/52 , H01L21/60 , H01L21/68 , H01L21/78 , H01L21/82
CPC分类号： H01L21/6835 , H01L21/02238 , H01L21/02255 , H01L21/30625 , H01L21/314 , H01L21/31654 , H01L21/31675 , H01L21/6836 , H01L21/78 , H01L2221/68327 , H01L2221/6834
摘要： A technique capable of stably releasing chips from a dicing tape, includes grinding a back surface of a semiconductor wafer, while adhering a pressure sensitive adhesive tape to a circuit forming surface of the semiconductor wafer formed with an integrated circuit, to achieve a predetermined thickness and forcibly oxidizing the back surface of the semiconductor wafer. Then, the pressure sensitive adhesive tape adhered to the circuit forming surface of the semiconductor wafer is released, and a dicing tape is adhered to the back surface of the semiconductor wafer. Further, the semiconductor wafer is divided by dicing it into individual chips, and then the back surface of the chip is pressed by way of the dicing tape, thereby releasing the chips from the dicing tape.
摘要翻译： 一种能够从切割带稳定地释放芯片的技术包括：将压敏粘合带粘附到形成有集成电路的半导体晶片的电路形成表面上，研磨半导体晶片的背面，以实现预定厚度， 强制氧化半导体晶片的背面。 然后，剥离粘附到半导体晶片的电路形成表面的压敏粘合带，并将切割带粘附到半导体晶片的背面。 此外，通过将半导体晶片切割成单独的芯片来分割半导体晶片，然后通过切割带对芯片的背面进行压制，从而从切割带释放芯片。
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公开(公告)号：US07759224B2
公开(公告)日：2010-07-20
申请号：US12170020
申请日：2008-07-09
申请人： Chuichi Miyazaki , Yoshiyuki Abe , Toshihide Uematsu , Minoru Kimura , Kazunari Suzuki , Masao Odagiri , Hideyuki Suga , Manabu Takata
发明人： Chuichi Miyazaki , Yoshiyuki Abe , Toshihide Uematsu , Minoru Kimura , Kazunari Suzuki , Masao Odagiri , Hideyuki Suga , Manabu Takata
IPC分类号： H01L21/00
CPC分类号： H01L21/6835 , H01L21/02238 , H01L21/02255 , H01L21/30625 , H01L21/314 , H01L21/31654 , H01L21/31675 , H01L21/6836 , H01L21/78 , H01L2221/68327 , H01L2221/6834
摘要： A technique capable of stably releasing chips from a dicing tape, includes grinding a back surface of a semiconductor wafer, while adhering a pressure sensitive adhesive tape to a circuit forming surface of the semiconductor wafer formed with an integrated circuit, to achieve a predetermined thickness and forcibly oxidizing the back surface of the semiconductor wafer. Then, the pressure sensitive adhesive tape adhered to the circuit forming surface of the semiconductor wafer is released, and a dicing tape is adhered to the back surface of the semiconductor wafer. Further, the semiconductor wafer is divided by dicing it into individual chips, and then the back surface of the chip is pressed by way of the dicing tape, thereby releasing the chips from the dicing tape.
摘要翻译： 一种能够从切割带稳定地释放芯片的技术包括：将压敏粘合带粘附到形成有集成电路的半导体晶片的电路形成表面上，研磨半导体晶片的背面，以实现预定厚度， 强制氧化半导体晶片的背面。 然后，剥离粘附到半导体晶片的电路形成表面的压敏粘合带，并将切割带粘附到半导体晶片的背面。 此外，通过将半导体晶片切割成单独的芯片来分割半导体晶片，然后通过切割带对芯片的背面进行压制，从而从切割带释放芯片。
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公开(公告)号：US08791574B2
公开(公告)日：2014-07-29
申请号：US13613031
申请日：2012-09-13
申请人： Toshihiko Akiba , Minoru Kimura , Masao Odagiri
发明人： Toshihiko Akiba , Minoru Kimura , Masao Odagiri
IPC分类号： H01L21/00
CPC分类号： H01L21/78 , B28D5/022 , H01L23/3121 , H01L24/48 , H01L24/49 , H01L2224/05554 , H01L2224/48095 , H01L2224/48247 , H01L2224/48465 , H01L2224/49171 , H01L2924/00014 , H01L2924/01013 , H01L2924/01019 , H01L2924/01029 , H01L2924/01078 , H01L2924/01079 , H01L2924/10156 , H01L2924/10157 , H01L2924/10253 , H01L2924/14 , H01L2924/181 , H01L2924/00 , H01L2924/00012 , H01L2224/45099 , H01L2224/45015 , H01L2924/207
摘要： In a manufacturing method of a semiconductor device having a multilevel interconnect layer including a low-k layer, a two-step cutting technique is used for dicing. After formation of a groove in a semiconductor wafer with a tapered blade, the groove is divided with a straight blade thinner than the groove width. The multilevel interconnect layer portion is cut while being covered with a tapered face and then the wafer is separated with a thin blade which is not brought into contact with the multilevel interconnect layer portion. The wafer can thus be diced without damaging a relatively fragile low-k layer.
摘要翻译： 在具有包括低k层的多层互连层的半导体器件的制造方法中，使用两步切割技术进行切割。 在具有锥形刀片的半导体晶片中形成凹槽之后，将沟槽分割成比凹槽宽度更薄的直线刀片。 多层互连层部分被切割，同时被锥形面覆盖，然后用不与多层互连层部分接触的薄片分离晶片。 因此，可以切割晶片而不破坏相对脆弱的低k层。
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公开(公告)号：US07452787B2
公开(公告)日：2008-11-18
申请号：US11020049
申请日：2004-12-23
申请人： Chuichi Miyazaki , Yoshiyuki Abe , Toshihide Uematsu , Minoru Kimura , Kazunari Suzuki , Masao Odagiri , Hideyuki Suga , Manabu Takata
发明人： Chuichi Miyazaki , Yoshiyuki Abe , Toshihide Uematsu , Minoru Kimura , Kazunari Suzuki , Masao Odagiri , Hideyuki Suga , Manabu Takata
IPC分类号： H01L21/00
CPC分类号： H01L21/6835 , H01L21/02238 , H01L21/02255 , H01L21/30625 , H01L21/314 , H01L21/31654 , H01L21/31675 , H01L21/6836 , H01L21/78 , H01L2221/68327 , H01L2221/6834
摘要： A technique capable of stably releasing chips from a dicing tape, includes grinding a back surface of a semiconductor wafer, while adhering a pressure sensitive adhesive tape to a circuit forming surface of the semiconductor wafer formed with an integrated circuit, to achieve a predetermined thickness and forcibly oxidizing the back surface of the semiconductor wafer. Then, the pressure sensitive adhesive tape adhered to the circuit forming surface of the semiconductor wafer is released, and a dicing tape is adhered to the back surface of the semiconductor wafer. Further, the semiconductor wafer is divided by dicing it into individual chips, and then the back surface of the chip is pressed by way of the dicing tape, thereby releasing the chips from the dicing tape.
摘要翻译： 一种能够从切割带稳定地释放芯片的技术包括：将压敏粘合带粘附到形成有集成电路的半导体晶片的电路形成表面上，研磨半导体晶片的背面，以实现预定厚度， 强制氧化半导体晶片的背面。 然后，剥离粘附到半导体晶片的电路形成表面的压敏粘合带，并将切割带粘附到半导体晶片的背面。 此外，通过将半导体晶片切割成单独的芯片来分割半导体晶片，然后通过切割带对芯片的背面进行压制，从而从切割带释放芯片。
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公开(公告)号：US20100181681A1
公开(公告)日：2010-07-22
申请号：US12690733
申请日：2010-01-20
申请人： Toshihiko AKIBA , Minoru KIMURA , Masao ODAGIRI
发明人： Toshihiko AKIBA , Minoru KIMURA , Masao ODAGIRI
IPC分类号： H01L23/522 , H01L21/304 , H01L21/56
CPC分类号： H01L21/78 , B28D5/022 , H01L23/3121 , H01L24/48 , H01L24/49 , H01L2224/05554 , H01L2224/48095 , H01L2224/48247 , H01L2224/48465 , H01L2224/49171 , H01L2924/00014 , H01L2924/01013 , H01L2924/01019 , H01L2924/01029 , H01L2924/01078 , H01L2924/01079 , H01L2924/10156 , H01L2924/10157 , H01L2924/10253 , H01L2924/14 , H01L2924/181 , H01L2924/00 , H01L2924/00012 , H01L2224/45099 , H01L2224/45015 , H01L2924/207
摘要： With a recent shrinking semiconductor process, insulating layers formed between interconnect layers are becoming thin. To avoid parasitic capacitance between them, materials of a low dielectric constant have been used for an insulating layer in a multilevel interconnect. Low-k materials, however, have low strength compared with the conventional insulating layers. Porous low-k materials are structurally fragile. The invention therefore provides a manufacturing method of a semiconductor device having a multilevel interconnect layer including a low-k layer. According to the method, in a two-step cutting system dicing in which after formation of a groove in a semiconductor water with a tapered blade, the groove is divided with a straight blade thinner than the groove width, the multilevel interconnect layer portion is cut while being covered with a tapered face and then the wafer is separated with a thin blade which is not brought into contact with the multilevel interconnect layer portion. The wafer can be diced without damaging a relatively fragile low-k layer.
摘要翻译： 随着半导体工艺的缩小，互连层之间形成的绝缘层变薄。 为了避免它们之间的寄生电容，低介电常数的材料已被用于多层互连中的绝缘层。 然而，与常规绝缘层相比，低k材料具有低强度。 多孔低k材料结构脆弱。 因此，本发明提供了具有包括低k层的多层互连层的半导体器件的制造方法。 根据该方法，在具有锥形叶片的半导体水中形成槽之后的两步切割系统切割中，将沟槽分割成比槽宽度薄的直线片，切割多层互连层部分 同时用锥形表面覆盖，然后用不与多层互连层部分接触的薄片分离晶片。 可以切割晶片，而不会损坏相对脆弱的低k层。
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