公开(公告)号：US08619930B2

公开(公告)日：2013-12-31

申请号：US13427209

申请日：2012-03-22

申请人： Masaru Takehara

发明人： Masaru Takehara

IPC分类号： H04L7/00 ,  H03K3/00

CPC分类号： H04L7/0338 ,  G11C7/1093 ,  G11C7/222

摘要： A synchronization circuit that synchronizes received data, includes: a determiner for determining whether or not data with a phase of a internal clock can be stably captured by the synchronization circuit, when the synchronization circuit accepts the data received from another device connected to the synchronization circuit with the phase of the internal clock of the synchronization circuit; a first flip-flop circuit accepting the data and the internal clock, capturing the data with the phase of the internal clock and synchronizing the data, when the determiner determines that the synchronization circuit can stably capture the data; a second flip-flop accepting the data and an inverted internal clock that has a phase obtained by inverting the phase of the internal clock, capturing the data with the phase of the inverted internal clock, and synchronizing the data, when the determiner determines that the synchronization circuit can not stably capture the data.

摘要翻译： 同步电路，其使接收到的数据同步，包括：确定器，用于当同步电路接受从连接到同步电路的另一设备接收到的数据时，确定是否可以由同步电路稳定地捕获具有内部时钟的相位的数据 同步电路的内部时钟的相位; 接收数据和内部时钟的第一触发器电路，当确定器确定同步电路可以稳定地捕获数据时，以内部时钟的相位捕获数据并同步数据; 接收数据的第二触发器和反相的内部时钟，其具有通过反相内部时钟的相位获得的相位，以反相的内部时钟的相位捕获数据，并且当该确定器确定 同步电路不能稳定地捕获数据。

公开(公告)号：US08539306B2

公开(公告)日：2013-09-17

申请号：US13150343

申请日：2011-06-01

申请人： Masaru Takehara

发明人： Masaru Takehara

IPC分类号： H03M13/05 ,  H03M13/27

CPC分类号： G06F11/10

摘要： A data processing circuit includes a receive circuit that receives data including a control bit for controlling a process of the data, a hold circuit that holds the received data, an error detection circuit that detects an error in the received data, a first correction circuit that corrects the received data when an error of the control bit in the received data is detected, and outputs the corrected data, and an output select circuit that outputs data held in the hold circuit when no error is detected in the control bit, and outputs the corrected data outputted from the first correction circuit when an error is detected in the control bit.

摘要翻译： 数据处理电路包括：接收电路，其接收包括用于控制数据处理的控制位的数据，保持接收数据的保持电路，检测接收到的数据中的错误的错误检测电路;第一校正电路， 当检测到接收到的数据中的控制位的错误时，校正接收到的数据并输出校正的数据;以及输出选择电路，当在控制位中没有检测到错误时，输出保持在保持电路中的数据，并输出 当在控制位中检测到错误时，从第一校正电路输出的校正数据。

公开(公告)号：US07882279B2

公开(公告)日：2011-02-01

申请号：US12382867

申请日：2009-03-25

申请人： Masaru Takehara

发明人： Masaru Takehara

IPC分类号： G06F13/10 ,  G06F13/38

CPC分类号： H03K19/01759

摘要： A bidirectional bus control circuit to which first and second direction signals instructing bus directions are input and which inputs and outputs a clock signal and data signal includes a first bidirectional buffer that switches an input or output direction of the clock signal in accordance with the second direction signal, a second bidirectional buffer that switches an input or output direction of the data signal in accordance with the second direction signal, and a data confirmation unit that confirms a data signal input to the second bidirectional buffer and invalidates the confirmation of the data signal in accordance with switching of the signal direction instructed by the first direction signal from the input direction to the output direction, the switching of the signal direction instructed by the first direction signal occurring before the switching of the signal direction instructed by the second direction.

摘要翻译： 输入第一和第二方向信号指示总线方向的双向总线控制电路，以及哪个输入和输出时钟信号和数据信号包括第一双向缓冲器，该第一双向缓冲器根据第二方向切换时钟信号的输入或输出方向 信号，根据第二方向信号切换数据信号的输入或输出方向的第二双向缓冲器，以及数据确认单元，其确认输入到第二双向缓冲器的数据信号，并使数据信号的确认无效 根据由第一方向信号从输入方向向输出方向指示的信号方向的切换，在由第二方向指示的信号方向切换之前由第一方向信号指示的信号方向的切换。

公开(公告)号：US06125424A

公开(公告)日：2000-09-26

申请号：US10795

申请日：1998-01-22

申请人： Shinpei Komatsu ,  Yumi Ishii ,  Tomohiro Hayashi ,  Shogo Shibazaki ,  Hiroyuki Itoh ,  Masaru Takehara

发明人： Shinpei Komatsu ,  Yumi Ishii ,  Tomohiro Hayashi ,  Shogo Shibazaki ,  Hiroyuki Itoh ,  Masaru Takehara

IPC分类号： G11C16/02 ,  G06F12/00 ,  G06F12/02 ,  G11C16/06 ,  G11C29/00 ,  G11C29/04 ,  G06F13/00

CPC分类号： G11C29/765 ,  G11C29/76 ,  G11C29/82

摘要： Data transferred from a host computer to a memory device is written into sectors whose addresses in a memory area are decoded by a decode table. Old data to be updated by the above data is erased or marked with erase flags. At a predetermined point of time, in order to create free areas, necessary data is evacuated to a primary memory media and unnecessary data indicated by erase flags is erased by a unit of predetermined memory size. Part of the memory media which has become defective is marked with a defect flag, and is replaced by an alternate area. In doing so, the decode table is rewritten to rearrange the memory area.

摘要翻译： 从主计算机传送到存储器件的数据被写入到存储器区域中的地址由解码表解码的扇区。 由上述数据更新的旧数据将被擦除或标记为擦除标志。 在预定的时间点，为了创建空闲区域，将必要的数据撤回到主存储介质，并且通过预定存储器大小的单位擦除由擦除标志指示的不必要的数据。 存在缺陷的存储介质的一部分标有缺陷标志，并被备用区域代替。 在这样做时，解码表被重写以重新排列存储器区域。

公开(公告)号：US6161163A

公开(公告)日：2000-12-12

申请号：US385998

申请日：1999-08-30

申请人： Shinpei Komatsu ,  Yumi Ishii ,  Tomohiro Hayashi ,  Shogo Shibazaki ,  Hiroyuki Itoh ,  Masaru Takehara

发明人： Shinpei Komatsu ,  Yumi Ishii ,  Tomohiro Hayashi ,  Shogo Shibazaki ,  Hiroyuki Itoh ,  Masaru Takehara

IPC分类号： G11C16/02 ,  G06F12/00 ,  G06F12/02 ,  G11C16/06 ,  G11C29/00 ,  G11C29/04 ,  G06F13/00

CPC分类号： G11C29/765 ,  G11C29/76 ,  G11C29/82

摘要： Data transferred from a host computer to a memory device is written into sectors whose addresses in a memory area are decoded by a decode table. Old data to be updated by the above data is erased or marked with erase flags. At a predetermined point of time, in order to create free areas, necessary data is evacuated to a primary memory media and unnecessary data indicated by erase flags is erased by a unit of predetermined memory size. Part of the memory media which has become defective is marked with a defect flag, and is replaced by an alternate area. In doing so, the decode table is rewritten to rearrange the memory area.

摘要翻译： 从主计算机传送到存储器件的数据被写入到存储器区域中的地址由解码表解码的扇区。 由上述数据更新的旧数据将被擦除或标记为擦除标志。 在预定的时间点，为了创建空闲区域，将必要的数据撤回到主存储介质，并且通过预定存储器大小的单位擦除由擦除标志指示的不必要的数据。 存在缺陷的存储介质的一部分标有缺陷标志，并被备用区域代替。 在这样做时，解码表被重写以重新排列存储器区域。

公开(公告)号：US5983312A

公开(公告)日：1999-11-09

申请号：US912692

申请日：1997-08-18

申请人： Shinpei Komatsu ,  Yumi Ishii ,  Tomohiro Hayashi ,  Shogo Shibazaki ,  Hiroyuki Itoh ,  Masaru Takehara

发明人： Shinpei Komatsu ,  Yumi Ishii ,  Tomohiro Hayashi ,  Shogo Shibazaki ,  Hiroyuki Itoh ,  Masaru Takehara

IPC分类号： G11C16/02 ,  G06F12/00 ,  G06F12/02 ,  G11C16/06 ,  G11C29/00 ,  G11C29/04

CPC分类号： G11C29/765 ,  G11C29/76 ,  G11C29/82

摘要： Data transferred from a host computer to a memory device is written into sectors whose addresses in a memory area are decoded by a decode table. Old data to be updated by the above data is erased or marked with erase flags. At a predetermined point of time, in order to create free areas, necessary data is evacuated to a primary memory media and unnecessary data indicated by erase flags is erased by a unit of predetermined memory size. Part of the memory media which has become defective is marked with a defect flag, and is replaced by an alternate area. In doing so, the decode table is rewritten to rearrange the memory area.

摘要翻译： 从主计算机传送到存储器件的数据被写入到存储器区域中的地址由解码表解码的扇区。 由上述数据更新的旧数据将被擦除或标记为擦除标志。 在预定的时间点，为了创建空闲区域，将必要的数据撤回到主存储介质，并且通过预定存储器大小的单位擦除由擦除标志指示的不必要的数据。 存在缺陷的存储介质的一部分标有缺陷标志，并被备用区域代替。 在这样做时，解码表被重写以重新排列存储器区域。

公开(公告)号：US20110320907A1

公开(公告)日：2011-12-29

申请号：US13150343

申请日：2011-06-01

申请人： Masaru TAKEHARA

发明人： Masaru TAKEHARA

IPC分类号： G06F11/10

CPC分类号： G06F11/10

摘要： A data processing circuit includes a receive circuit that receives data including a control bit for controlling a process of the data, a hold circuit that holds the received data, an error detection circuit that detects an error in the received data, a first correction circuit that corrects the received data when an error of the control bit in the received data is detected, and outputs the corrected data, and an output select circuit that outputs data held in the hold circuit when no error is detected in the control bit, and outputs the corrected data outputted from the first correction circuit when an error is detected in the control bit.

摘要翻译： 数据处理电路包括：接收电路，其接收包括用于控制数据处理的控制位的数据，保持接收数据的保持电路，检测接收到的数据中的错误的错误检测电路;第一校正电路， 当检测到接收到的数据中的控制位的错误时，校正接收到的数据并输出校正的数据;以及输出选择电路，当在控制位中没有检测到错误时，输出保持在保持电路中的数据，并输出 当在控制位中检测到错误时，从第一校正电路输出的校正数据。

公开(公告)号：US07257666B2

公开(公告)日：2007-08-14

申请号：US10788336

申请日：2004-03-01

申请人： Shinpei Komatsu ,  Yumi Ishii ,  Tomohiro Hayashi ,  Shogo Shibazaki ,  Hiroyuki Itoh ,  Masaru Takehara

发明人： Shinpei Komatsu ,  Yumi Ishii ,  Tomohiro Hayashi ,  Shogo Shibazaki ,  Hiroyuki Itoh ,  Masaru Takehara

IPC分类号： G06F12/00 ,  G06F11/00

CPC分类号： G11C29/765 ,  G11C29/76 ,  G11C29/82

摘要： Data transferred from a host computer to a memory device is written into sectors whose addresses in a memory area are decoded by a decode table. Old data to be updated by the above data is erased or marked with erase flags. At a predetermined point of time, in order to create free areas, necessary data is evacuated to a primary memory media and unnecessary data indicated by erase flags is erased by a unit of predetermined memory size. Part of the memory media which has become defective is marked with a defect flag, and is replaced by an alternate area. In doing so, the decode table is rewritten to arrange the memory area.

摘要翻译： 从主计算机传送到存储器件的数据被写入到存储器区域中的地址由解码表解码的扇区。 由上述数据更新的旧数据将被擦除或标记为擦除标志。 在预定的时间点，为了创建空闲区域，将必要的数据撤回到主存储介质，并且通过预定存储器大小的单位擦除由擦除标志指示的不必要的数据。 存在缺陷的存储介质的一部分标有缺陷标志，并被备用区域代替。 在这样做时，解码表被重写以排列存储器区域。

公开(公告)号：US06766409B2

公开(公告)日：2004-07-20

申请号：US10446810

申请日：2003-05-29

申请人： Shinpei Komatsu ,  Yumi Ishii ,  Tomohiro Hayashi ,  Shogo Shibazaki ,  Hiroyuki Itoh ,  Masaru Takehara

发明人： Shinpei Komatsu ,  Yumi Ishii ,  Tomohiro Hayashi ,  Shogo Shibazaki ,  Hiroyuki Itoh ,  Masaru Takehara

IPC分类号： G06F1300

CPC分类号： G11C29/765 ,  G11C29/76 ,  G11C29/82

摘要： Data transferred from a host computer to a memory device is written into sectors whose addresses in a memory area are decoded by a decode table. Old data to be updated by the above data is erased or marked with erase flags. At a predetermined point of time, in order to create free areas, necessary data is evacuated to a primary memory media and unnecessary data indicated by erase flags is erased by a unit of predetermined memory size. Part of the memory media which has become defective is marked with a defect flag, and is replaced by an alternate area. In doing so, the decode table is rewritten to arrange the memory area.

公开(公告)号：US20120300882A1

公开(公告)日：2012-11-29

申请号：US13427209

申请日：2012-03-22

申请人： Masaru TAKEHARA

发明人： Masaru TAKEHARA

IPC分类号： H04L7/033

CPC分类号： H04L7/0338 ,  G11C7/1093 ,  G11C7/222

摘要： A synchronization circuit that synchronizes received data, includes: a determiner for determining whether or not data with a phase of a internal clock can be stably captured by the synchronization circuit, when the synchronization circuit accepts the data received from another device connected to the synchronization circuit with the phase of the internal clock of the synchronization circuit; a first flip-flop circuit accepting the data and the internal clock, capturing the data with the phase of the internal clock and synchronizing the data, when the determiner determines that the synchronization circuit can stably capture the data; a second flip-flop accepting the data and an inverted internal clock that has a phase obtained by inverting the phase of the internal clock, capturing the data with the phase of the inverted internal clock, and synchronizing the data, when the determiner determines that the synchronization circuit can not stably capture the data.

摘要翻译： 同步电路，其使接收到的数据同步，包括：确定器，用于当同步电路接受从连接到同步电路的另一设备接收的数据时，确定是否可以由同步电路稳定地捕获具有内部时钟的相位的数据 同步电路的内部时钟的相位; 接收数据和内部时钟的第一触发器电路，当确定器确定同步电路可以稳定地捕获数据时，以内部时钟的相位捕获数据并同步数据; 接收数据的第二触发器和反相的内部时钟，其具有通过反相内部时钟的相位获得的相位，以反相的内部时钟的相位捕获数据，并且当该确定器确定 同步电路不能稳定地捕获数据。