公开(公告)号：US20080148343A1

公开(公告)日：2008-06-19

申请号：US11612814

申请日：2006-12-19

申请人： Masayoshi Taniguchi

发明人： Masayoshi Taniguchi

IPC分类号： G06F17/00 ,  G06F11/00

CPC分类号： G06F21/71 ,  G06F11/2236

摘要： A system-on-chip (SoC) application-specific integrated circuit (ASIC) includes a processor, a finite state machine (FSM), and a security mechanism. The processor exposes debugging ports. The FSM permits permit instructions to be externally input to the debugging ports and data to be externally output from the debugging ports. The security mechanism prevents access to at least a subset of the debugging ports unless a security code externally input via a security interface of the security mechanism matches a predetermined internally stored security code. Additionally or alternatively, the security mechanism prevents at least a subset of the instructions from being processed unless a security code externally input via a security code instruction asserted on the debugging ports matches the predetermined internally stored security code.

摘要翻译： 片上系统（SoC）专用集成电路（ASIC）包括处理器，有限状态机（FSM）和安全机制。 处理器暴露调试端口。 FSM允许外部向调试端口输入允许指令，并从调试端口外部输出数据。 安全机制防止访问调试端口的至少一个子集，除非通过安全机制的安全接口外部输入的安全码与预定的内部存储的安全码匹配。 另外或替代地，安全机制防止指令的至少一个子集被处理，除非通过在调试端口上断言的安全代码指令外部输入的安全码与预定的内部存储的安全码匹配。

公开(公告)号：US5878272A

公开(公告)日：1999-03-02

申请号：US710453

申请日：1996-09-18

申请人： Takashi Yanagisawa ,  Masayoshi Taniguchi ,  Masayoshi Nakano

发明人： Takashi Yanagisawa ,  Masayoshi Taniguchi ,  Masayoshi Nakano

IPC分类号： G06F13/28 ,  G06F13/42

CPC分类号： G06F13/28

摘要： A computer system has a central processing unit ("CPU") and a plurality of peripheral devices. A bus interconnects the CPU and the peripheral devices. Command signals are transmitted over the bus including an initiator ready signal ("IRDY"), a device select signal ("DEVSEL"), and a target ready signal ("TRDY"). First and second direct memory access devices ("DMA") are connected to the bus and assigned the same address space. First and second switches selectively connect and disconnect the DEVSEL and TRDY signals that are output from the first and second DMA devices, respectively. Controller logic receives the DEVSEL and TRDY signals and directs the opening and closing of the first and second switches.

摘要翻译： 计算机系统具有中央处理单元（“CPU”）和多个外围设备。 总线连接CPU和外围设备。 命令信号通过总线发送，包括启动器就绪信号（“IRDY”），设备选择信号（“DEVSEL”）和目标就绪信号（“TRDY”）。 第一和第二直接存储器访问设备（“DMA”）连接到总线并分配相同的地址空间。 第一和第二开关分别选择性地连接和断开从第一和第二DMA设备输出的DEVSEL和TRDY信号。 控制器逻辑接收DEVSEL和TRDY信号，并指示第一和第二开关的打开和关闭。

公开(公告)号：US07337366B2

公开(公告)日：2008-02-26

申请号：US10905139

申请日：2004-12-17

申请人： Masayoshi Taniguchi

发明人： Masayoshi Taniguchi

IPC分类号： G06F11/00

CPC分类号： G01R31/31705 ,  G01R31/318536 ,  G01R31/318555 ,  G06F21/79 ,  G06F21/85 ,  G06F2221/2105 ,  G06F2221/2149 ,  G11C7/24 ,  G11C2029/0401 ,  G11C2029/0407 ,  G11C2029/3202

摘要： A microcomputer, a method for protecting memory and a method for performing debugging is provided including a TAP controller and instruction decoder for monitoring an external input for a processor, internal registers and comparators for determining whether or not the destination address of an access by the processor to ROM and SRAM is within a predetermined protected area, and internal registers and multiplexers as access control means. If a control instruction for the processor has been detected and an execution of an access from the processor to the protected area has been detected, the destination address of the access is replaced with addresses of a ROM and SRAM of an additional circuitry block that have been prepared by developers.

摘要翻译： 提供一种微机，保护存储器的方法和执行调试的方法，包括TAP控制器和用于监视处理器的外部输入的指令解码器，内部寄存器和比较器，用于确定处理器的访问的目的地地址 ROM和SRAM位于预定保护区内，内部寄存器和多路复用器作为访问控制装置。 如果已经检测到用于处理器的控制指令并且已经检测到从处理器到保护区域的访问的执行，则访问的目的地地址被替换为已经被附加的电路块的ROM和SRAM的地址 由开发商准备。

公开(公告)号：US20050154947A1

公开(公告)日：2005-07-14

申请号：US10905227

申请日：2004-12-22

申请人： Masayoshi Taniguchi

发明人： Masayoshi Taniguchi

IPC分类号： G06F11/22 ,  G01R31/317 ,  G06F11/267 ,  G06F15/78 ,  G01R31/28

CPC分类号： G06F11/267 ,  G01R31/31705

摘要： The System on a Chip (SoC) according to the present invention provides debugging by reading or rewriting the contents of an arbitrary register within an SoC by a level-sensitive scan design (LSSD) scan test, and includes a scan chain for scan tests that connects a plurality of latch circuits in chain form and a debug circuit for, while performing a scan test on the scan chain, specifying a specific latch circuit constituting the scan chain and reading data from the latch circuit. The scan chain gives output back to the input of the first latch circuit, thus forming a feedback loop. There exist a plurality of such scan chains, each consisting of the same number of latch circuits, including latch circuits for performing a scan test and dummy latch circuits for making the number of latch circuits constituting the scan chain identical among all of the scan chains.

摘要翻译： 根据本发明的片上系统（SoC）通过读取或重写SoC内的任意寄存器的内容，通过水平敏感扫描设计（LSSD）扫描测试来提供调试，并且包括用于扫描测试的扫描链， 以链式形式连接多个锁存电路和调试电路，用于在扫描链上执行扫描测试，指定构成扫描链的特定锁存电路并从锁存电路读取数据。 扫描链将输出返回到第一锁存电路的输入，从而形成反馈回路。 存在多个这样的扫描链，每个扫描链由相同数量的锁存电路组成，包括用于执行扫描测试的锁存电路和用于使构成扫描链的锁存电路的数量在所有扫描链中相同的虚拟锁存电路。

公开(公告)号：US20090097335A1

公开(公告)日：2009-04-16

申请号：US12330936

申请日：2008-12-09

申请人： MASAYOSHI TANIGUCHI ,  ISAMU MASHIMA ,  JUN USAMI

发明人： MASAYOSHI TANIGUCHI ,  ISAMU MASHIMA ,  JUN USAMI

IPC分类号： G11C7/00 ,  G11C29/00 ,  G11C5/14 ,  G11C17/16

CPC分类号： G11C29/789

摘要： A method and apparatus to configure redundant memory elements in a system on a chip (SoC) having discrete voltage domains (islands). A plurality of memories are provided for each voltage island, each containing redundancy elements or having the capability to access redundant memory elements in a neighboring voltage domain; a fuse cell stores configuration information for controlling the switching of memory elements of the plurality of memories; a shift register receives and retains configuration information on a memory array from the fuse cell corresponding to each memory; and a control circuit directs operation of the shift register. The shift register includes a shift portion for receiving the data of the configuration information and transferring the data to another shift register, and a latch portion for retaining the data inputted to the shift portion. The control circuit controls whether or not the data of the shift register, which is inputted to the shift portion, is to be retained in the latch portion.

摘要翻译： 一种在具有离散电压域（岛）的芯片（SoC）上的系统中配置冗余存储器元件的方法和装置。 为每个电压岛提供多个存储器，每个电压岛包含冗余元件或具有访问相邻电压域中的冗余存储器元件的能力; 熔丝单元存储用于控制多个存储器的存储元件的切换的配置信息; 移位寄存器从对应于每个存储器的熔丝单元接收并保存关于存储器阵列的配置信息; 并且控制电路指示移位寄存器的操作。 移位寄存器包括用于接收配置信息的数据并将数据传送到另一移位寄存器的移位部分，以及用于保存输入到移位部分的数据的锁存部分。 控制电路控制输入到移位部分的移位寄存器的数据是否被保留在锁存部分中。

公开(公告)号：US20050138481A1

公开(公告)日：2005-06-23

申请号：US10905139

申请日：2004-12-17

申请人： Masayoshi Taniguchi

发明人： Masayoshi Taniguchi

IPC分类号： G01R31/28 ,  G06F11/00 ,  G06F11/22 ,  G06F12/14 ,  G06F15/78

CPC分类号： G01R31/31705 ,  G01R31/318536 ,  G01R31/318555 ,  G06F21/79 ,  G06F21/85 ,  G06F2221/2105 ,  G06F2221/2149 ,  G11C7/24 ,  G11C2029/0401 ,  G11C2029/0407 ,  G11C2029/3202

摘要： A microcomputer, a method for protecting memory and a method for performing debugging is provided including a TAP controller and instruction decoder for monitoring an external input for a processor, internal registers and comparators for determining whether or not the destination address of an access by the processor to ROM and SRAM is within a predetermined protected area, and internal registers and multiplexers as access control means. If a control instruction for the processor has been detected and an execution of an access from the processor to the protected area has been detected, the destination address of the access is replaced with addresses of a ROM and SRAM of an additional circuitry block that have been prepared by developers.

摘要翻译： 提供一种微机，保护存储器的方法和执行调试的方法，包括TAP控制器和用于监视处理器的外部输入的指令解码器，内部寄存器和比较器，用于确定处理器的访问的目的地地址 ROM和SRAM位于预定保护区内，内部寄存器和多路复用器作为访问控制装置。 如果已经检测到用于处理器的控制指令并且已经检测到从处理器到保护区域的访问的执行，则访问的目的地地址被替换为已经被附加的电路块的ROM和SRAM的地址 由开发商准备。

公开(公告)号：US07477564B2

公开(公告)日：2009-01-13

申请号：US11275247

申请日：2005-12-20

申请人： Masayoshi Taniguchi ,  Isamu Mashima ,  Jun Usami

发明人： Masayoshi Taniguchi ,  Isamu Mashima ,  Jun Usami

IPC分类号： G11C17/18

CPC分类号： G11C29/789

摘要： A method and apparatus to configure redundant memory elements in a system on a chip (SoC) having discrete voltage domains (islands). A plurality of memories are provided for each voltage island, each containing redundancy elements or having the capability to access redundant memory elements in a neighboring voltage domain; a fuse cell stores configuration information for controlling the switching of memory elements of the plurality of memories; a shift register receives and retains configuration information on a memory array from the fuse cell corresponding to each memory; and a control circuit directs operation of the shift register. The shift register includes a shift portion for receiving the data of the configuration information and transferring the data to another shift register, and a latch portion for retaining the data inputted to the shift portion. The control circuit controls whether or not the data of the shift register, which is inputted to the shift portion, is to be retained in the latch portion.

摘要翻译： 一种在具有离散电压域（岛）的芯片（SoC）上的系统中配置冗余存储器元件的方法和装置。 为每个电压岛提供多个存储器，每个电压岛包含冗余元件或具有访问相邻电压域中的冗余存储器元件的能力; 熔丝单元存储用于控制多个存储器的存储元件的切换的配置信息; 移位寄存器从对应于每个存储器的熔丝单元接收并保存关于存储器阵列的配置信息; 并且控制电路指示移位寄存器的操作。 移位寄存器包括用于接收配置信息的数据并将数据传送到另一移位寄存器的移位部分，以及用于保存输入到移位部分的数据的锁存部分。 控制电路控制输入到移位部分的移位寄存器的数据是否被保留在锁存部分中。

公开(公告)号：US20070109882A1

公开(公告)日：2007-05-17

申请号：US11275247

申请日：2005-12-20

申请人： Masayoshi Taniguchi ,  Isamu Mashima ,  Jun Usami

发明人： Masayoshi Taniguchi ,  Isamu Mashima ,  Jun Usami

IPC分类号： G11C29/00

CPC分类号： G11C29/789

摘要： A method and apparatus to configure redundant memory elements in a system on a chip (SoC) having discrete voltage domains (islands). A plurality of memories are provided for each voltage island, each containing redundancy elements or having the capability to access redundant memory elements in a neighboring voltage domain; a fuse cell stores configuration information for controlling the switching of memory elements of the plurality of memories; a shift register receives and retains configuration information on a memory array from the fuse cell corresponding to each memory; and a control circuit directs operation of the shift register. The shift register includes a shift portion for receiving the data of the configuration information and transferring the data to another shift register, and a latch portion for retaining the data inputted to the shift portion. The control circuit controls whether or not the data of the shift register, which is inputted to the shift portion, is to be retained in the latch portion.

摘要翻译： 一种在具有离散电压域（岛）的芯片（SoC）上的系统中配置冗余存储器元件的方法和装置。 为每个电压岛提供多个存储器，每个电压岛包含冗余元件或具有访问相邻电压域中的冗余存储器元件的能力; 熔丝单元存储用于控制多个存储器的存储元件的切换的配置信息; 移位寄存器从对应于每个存储器的熔丝单元接收并保存关于存储器阵列的配置信息; 并且控制电路指示移位寄存器的操作。 移位寄存器包括用于接收配置信息的数据并将数据传送到另一移位寄存器的移位部分，以及用于保存输入到移位部分的数据的锁存部分。 控制电路控制输入到移位部分的移位寄存器的数据是否被保留在锁存部分中。

公开(公告)号：US06209042B1

公开(公告)日：2001-03-27

申请号：US09122283

申请日：1998-07-24

申请人： Takashi Yanagisawa ,  Masayoshi Taniguchi ,  Masayoshi Nakano

发明人： Takashi Yanagisawa ,  Masayoshi Taniguchi ,  Masayoshi Nakano

IPC分类号： G06F300

CPC分类号： G06F13/28

摘要： A computer system has a central processing unit (“CPU”) and a plurality of peripheral devices. A bus interconnects the CPU and the peripheral devices. Command signals are transmitted over the bus including an initiator ready signal (“IRDY”), a device select signal (“DEVSEL”) and a target ready signal (“TRDY”). First and second direct memory access devices (“DMA”) are connected to the bus and assigned the same address space. First and second switches selectively connect and disconnect the DEVSEL and TRDY signals that are output from the first and second DMA devices, respectively. Controller logic receives the DEVSEL and TRDY signals and directs the opening and closing of the first and second switches.

摘要翻译： 计算机系统具有中央处理单元（“CPU”）和多个外围设备。 总线连接CPU和外围设备。 命令信号通过总线发送，包括启动器就绪信号（“IRDY”），设备选择信号（“DEVSEL”）和目标就绪信号（“TRDY”）。 第一和第二直接存储器访问设备（“DMA”）连接到总线并分配相同的地址空间。 第一和第二开关分别选择性地连接和断开从第一和第二DMA设备输出的DEVSEL和TRDY信号。 控制器逻辑接收DEVSEL和TRDY信号，并指示第一和第二开关的打开和关闭。

公开(公告)号：US07859934B2

公开(公告)日：2010-12-28

申请号：US12330936

申请日：2008-12-09

申请人： Masayoshi Taniguchi ,  Isamu Mashima ,  Jun Usami

发明人： Masayoshi Taniguchi ,  Isamu Mashima ,  Jun Usami

IPC分类号： G11C17/18

CPC分类号： G11C29/789

摘要： A method and apparatus to configure redundant memory elements in a system on a chip (SoC) having discrete voltage domains (islands). A plurality of memories are provided for each voltage island, each containing redundancy elements or having the capability to access redundant memory elements in a neighboring voltage domain; a fuse cell stores configuration information for controlling the switching of memory elements of the plurality of memories; a shift register receives and retains configuration information on a memory array from the fuse cell corresponding to each memory; and a control circuit directs operation of the shift register. The shift register includes a shift portion for receiving the data of the configuration information and transferring the data to another shift register, and a latch portion for retaining the data inputted to the shift portion. The control circuit controls whether or not the data of the shift register, which is inputted to the shift portion, is to be retained in the latch portion.

摘要翻译： 一种在具有离散电压域（岛）的芯片（SoC）上的系统中配置冗余存储器元件的方法和装置。 为每个电压岛提供多个存储器，每个电压岛包含冗余元件或具有访问相邻电压域中的冗余存储器元件的能力; 熔丝单元存储用于控制多个存储器的存储元件的切换的配置信息; 移位寄存器从对应于每个存储器的熔丝单元接收并保存关于存储器阵列的配置信息; 并且控制电路指示移位寄存器的操作。 移位寄存器包括用于接收配置信息的数据并将数据传送到另一移位寄存器的移位部分，以及用于保存输入到移位部分的数据的锁存部分。 控制电路控制输入到移位部分的移位寄存器的数据是否被保留在锁存部分中。