公开(公告)号：US06549473B2

公开(公告)日：2003-04-15

申请号：US09871234

申请日：2001-05-30

申请人： Paolo Rolandi ,  Massimo Montanaro ,  Giorgio Oddone

发明人： Paolo Rolandi ,  Massimo Montanaro ,  Giorgio Oddone

IPC分类号： G11C1604

CPC分类号： G11C16/28 ,  G11C11/5621 ,  G11C11/5642 ,  G11C2211/5634

摘要： A circuit structure for reading data contained in an electrically programmable/erasable integrated non-volatile memory device includes a matrix of memory cells and at least one reference cell for comparison with a memory cell during a reading phase. The reference cell is incorporated in a reference cells sub-matrix which is structurally independent of the matrix of memory cells. Also provided is a conduction path between the matrix and the sub-matrix, which path includes bit lines of the sub-matrix of reference cells extended continuously into the matrix of memory cells.

公开(公告)号：US06476664B2

公开(公告)日：2002-11-05

申请号：US09823262

申请日：2001-03-29

申请人： Paolo Rolandi ,  Massimo Montanaro ,  Giorgio Oddone

发明人： Paolo Rolandi ,  Massimo Montanaro ,  Giorgio Oddone

IPC分类号： G05F110

CPC分类号： G11C16/12

摘要： The integrated device comprises a PMOS transistor and a voltage selector having an output connected to the bulk terminal of the PMOS transistor. The voltage selector comprises an input stage supplying a supply voltage or a programming voltage according to whether the device is in a reading step or in a programming step; a comparator connected to the output of the input stage, receiving a boosted voltage, and generating a first control signal, the state whereof depends upon the comparison of the voltages at the inputs of the comparator; a logic circuit connected to the output of the comparator and generating a second control signal, the state whereof depends upon the state of the first control signal and of a third-level signal; and a switching circuit controlled by the first control signal, by the second control signal, and by the third-level signal and supplying each time the highest among the supply voltage, the boosted voltage, and the programming voltage.

摘要翻译： 集成器件包括PMOS晶体管和具有连接到PMOS晶体管的体端的输出的电压选择器。 电压选择器包括输入级，其根据该器件是处于读取步骤还是在编程步骤中提供电源电压或编程电压; 连接到输入级的输出的比较器，接收升高的电压，并产生第一控制信号，其状态取决于比较器输入端的电压的比较; 连接到比较器的输出并产生第二控制信号的逻辑电路，其状态取决于第一控制信号和第三电平信号的状态; 以及由第一控制信号，第二控制信号和第三电平信号控制的开关电路，并且每一时刻提供电源电压，升压电压和编程电压中的最高值。

公开(公告)号：US07136305B2

公开(公告)日：2006-11-14

申请号：US10913788

申请日：2004-08-06

申请人： Mauro Pagliato ,  Massimo Montanaro ,  Paolo Rolandi

发明人： Mauro Pagliato ,  Massimo Montanaro ,  Paolo Rolandi

IPC分类号： G11C16/06 ,  G11C7/02

CPC分类号： G11C11/5642 ,  G11C7/06 ,  G11C7/062 ,  G11C7/067 ,  G11C16/28

摘要： A sense amplifier is provided that includes a measure branch receiving an input current to be detected, a reference branch receiving a reference current, and an equalizing circuit including a comparator. The equalizing circuit selectively equalizes a measure node of the measure branch with a reference node of the reference branch, and the comparator compares a voltage at the measure node of the measure branch with a voltage at the reference node of the reference branch. The equalizing circuit is such that, when activated, equalization of the measure node with the reference node is virtual and substantially does not involve a flow of current between the measure node and the reference node of the reference branch. The sense amplifier is particularly suited for reading memory cells of a semiconductor memory. Also provided is a method for sensing an input current.

摘要翻译： 提供了一种读出放大器，其包括接收待检测的输入电流的测量分支，接收参考电流的参考分支和包括比较器的均衡电路。 均衡电路选择性地将测量分支的测量节点与参考分支的参考节点相等，并且比较器将测量分支的测量节点处的电压与参考分支的参考节点处的电压进行比较。 均衡电路使得当被激活时，具有参考节点的测量节点的均衡是虚拟的并且基本上不涉及测量节点和参考分支的参考节点之间的电流。 读出放大器特别适用于读取半导体存储器的存储单元。 还提供了用于感测输入电流的方法。

公开(公告)号：US6075718A

公开(公告)日：2000-06-13

申请号：US39588

申请日：1998-03-16

申请人： Marco Fontana ,  Antonio Barcella ,  Massimo Montanaro ,  Carmelo Paolino

发明人： Marco Fontana ,  Antonio Barcella ,  Massimo Montanaro ,  Carmelo Paolino

IPC分类号： G11C16/26 ,  G11C17/00

CPC分类号： G11C16/26

摘要： The method comprises the steps of detecting the trailing edge of an initialization signal, and generating a read bias signal and a read activation signal for the cell, when the trailing edge of the initialization signal is detected. The signals of read bias and read activation have a ramp-like leading edge and both signals are disabled when reading of the cell is completed. Thereby, phenomena of soft-writing of the cell are avoided, and risks of erroneous readings are reduced.

摘要翻译： 该方法包括以下步骤：当检测到初始化信号的后沿时，检测初始化信号的后沿，以及产生用于该单元的读取偏置信号和读取激活信号。 读取偏置和读取激活的信号具有斜坡状的前沿，当读取单元格完成时，两个信号都被禁止。 从而避免了对单元进行软写入的现象，并且降低了错误读数的风险。

公开(公告)号：US5796275A

公开(公告)日：1998-08-18

申请号：US791700

申请日：1997-01-30

申请人： Paolo Rolandi ,  Massimo Montanaro

发明人： Paolo Rolandi ,  Massimo Montanaro

IPC分类号： G01R19/165 ,  H03K17/30 ,  H03K5/153

CPC分类号： H03K17/302 ,  G01R19/16519

摘要： The circuit, in accordance with the present invention is for detecting the presence at a signal input of a high voltage higher than a predetermined value and signaling it to a signal output through a logical type signal. The circuit comprises one or more first transistors of MOS type and of a predetermined conductivity type, each being diode-connected and having its body terminal connected to the source terminal, and having principal conduction paths connected in series for current conduction between a first node and a ground input. The circuit also includes two or more second transistors of the MOS type and of the same conductivity type, with each one being diode-connected and having its body terminal connected to the source terminal and having principal conduction paths connected in series for current conduction between the signal input and the first node. At least one first logical inverter of the CMOS type has its input connected to the first node and its output coupled to the signal output and is also connected for power supply to a power supply input and to the ground input.

摘要翻译： 根据本发明的电路用于检测在高于预定值的高电压的信号输入处的存在并将其信号通过逻辑类型信号输出的信号。 电路包括一个或多个MOS型和预定导电类型的第一晶体管，每个第二晶体管是二极管连接的，其主体端子连接到源极端子，并且具有串联连接的主要导电路径，用于在第一节点和 地面输入。 该电路还包括两个或更多个MOS型和相同导电类型的第二晶体管，其中每一个二极管连接并且其主体端子连接到源极端子并且具有串联连接的主要导电路径，用于在 信号输入和第一个节点。 CMOS型的至少一个第一逻辑逆变器的输入连接到第一节点，其输出耦合到信号输出，并且还被连接用于电源输入和接地输入。

公开(公告)号：US20050063236A1

公开(公告)日：2005-03-24

申请号：US10913788

申请日：2004-08-06

申请人： Mauro Pagliato ,  Massimo Montanaro ,  Paolo Rolandi

发明人： Mauro Pagliato ,  Massimo Montanaro ,  Paolo Rolandi

IPC分类号： G11C7/06 ,  G11C11/56 ,  G11C16/28 ,  G11C11/34

CPC分类号： G11C11/5642 ,  G11C7/06 ,  G11C7/062 ,  G11C7/067 ,  G11C16/28

摘要： A sense amplifier is provided that includes a measure branch receiving an input current to be detected, a reference branch receiving a reference current, equalizing means, and a comparator. The equalizing means selectively equalizes a measure node of the measure branch with a reference node of the reference branch, and the comparator compares a voltage at the measure node of the measure branch with a voltage at the reference node of the reference branch. The equalizing means are such that, when activated, equalization of the measure node with the reference node is virtual and substantially does not involve a flow of current between the measure node and the reference node of the reference branch. The sense amplifier is particularly suited for reading memory cells of a semiconductor memory. Also provided is a method for sensing an input current.

摘要翻译： 提供了一种读出放大器，其包括接收待检测的输入电流的测量分支，接收参考电流的参考分支，均衡装置和比较器。 均衡装置选择性地将测量分支的测量节点与参考分支的参考节点进行均衡，并且比较器将测量分支的测量节点处的电压与参考分支的参考节点处的电压进行比较。 均衡装置使得当激活时，具有参考节点的测量节点的均衡是虚拟的并且基本上不涉及测量节点和参考分支的参考节点之间的电流。 读出放大器特别适用于读取半导体存储器的存储单元。 还提供了用于感测输入电流的方法。

公开(公告)号：US06657895B2

公开(公告)日：2003-12-02

申请号：US10118660

申请日：2002-04-08

申请人： Mauro Pagliato ,  Paolo Rolandi ,  Massimo Montanaro

发明人： Mauro Pagliato ,  Paolo Rolandi ,  Massimo Montanaro

IPC分类号： G11C1600

CPC分类号： G11C11/5642 ,  G11C11/56 ,  G11C11/5621 ,  G11C2211/5632

摘要： Described herein is an asynchronous serial dichotomic sense amplifier comprising a first comparator stage having a first input receiving the cell current flowing in the multilevel memory cell, the content of which is to be read, a second input receiving a first reference current, and an output supplying the first of the bits stored in the multilevel memory cell; a multiplexer stage having a selection input connected to the output of the first comparator stage, a first signal input receiving a second reference current, a second signal input receiving a third reference current, and a signal output selectively connectable to the first or the second signal input depending on the logic level present on the selection input; and a second comparator stage having a first input receiving the cell current, a second input connected to the signal output of the multiplexer stage, and an output supplying the second of the bits stored in the multilevel memory cell.

公开(公告)号：US06429634B2

公开(公告)日：2002-08-06

申请号：US09778330

申请日：2001-02-06

申请人： Paolo Rolandi ,  Massimo Montanaro ,  Giorgio Oddone

发明人： Paolo Rolandi ,  Massimo Montanaro ,  Giorgio Oddone

IPC分类号： G05F140

CPC分类号： H02M3/07

摘要： A voltage boosting device for speeding power-up of multilevel nonvolatile memories, including a voltage regulator and a charge pump and having an output terminal; the voltage regulator having a regulation terminal connected to the output terminal, and an output supplying a control voltage; the read charge pump having an output connected to the output terminal and supplying a read voltage. The device further includes an enable circuit connected to the output and having a pump enable output connected to a charge pump enable terminal and supplying a pump enable signal. The pump enable signal is set at a first logic level so as to activate the charge pump when the read voltage is lower than a nominal value. In addition, the device generates a power-up sync signal which activates a read operation when the read voltage reaches its nominal value and a chip enable signal is set at an active value.

摘要翻译： 一种用于加速包括电压调节器和电荷泵并具有输出端子的多级非易失性存储器的加电的升压装置; 所述调压器具有连接到所述输出端子的调节端子和提供控制电压的输出; 读取电荷泵具有连接到输出端子并提供读取电压的输出。 该装置还包括连接到输出端的使能电路，并且具有连接到电荷泵使能端的泵使能输出端并提供泵使能信号。 泵使能信号被设置在第一逻辑电平，以便当读取电压低于额定值时激活电荷泵。 此外，器件产生上电同步信号，当读取电压达到其标称值并且芯片使能信号被设置为有效值时，其启动读取操作。

公开(公告)号：US06301157B1

公开(公告)日：2001-10-09

申请号：US09415024

申请日：1999-10-07

申请人： Marco Riva ,  Paolo Rolandi ,  Massimo Montanaro

发明人： Marco Riva ,  Paolo Rolandi ,  Massimo Montanaro

IPC分类号： G11C1606

CPC分类号： G11C29/50 ,  G06F2201/81 ,  G11C11/56 ,  G11C11/5642 ,  G11C2029/5006 ,  G11C2211/5634

摘要： A method for testing memory cells, and in particular virgin memory cells, in a multilevel memory device having a plurality of memory cells. The method includes reading the individual memory cells that constitute a memory device and comparing each one of these memory cells with at least one reference memory cell at a time, so as to determine whether the threshold of the memory cells is lower than the threshold of the at least one reference memory cell or not; determining the number of the memory cells whose threshold is higher than the threshold of the at least one reference cell; the at least one reference memory cell being chosen with a gradually higher threshold; when the number of memory cells whose threshold is higher than a given reference threshold is found to be sufficiently lower than the number of redundancy memory cells provided in the memory device, assuming the given reference threshold as lower reference threshold for the memory device, determining a statistical distribution of the thresholds of the memory cells.

摘要翻译： 一种用于在具有多个存储器单元的多电平存储器件中测试存储器单元，特别是处理存储器单元的方法。 该方法包括读取构成存储器件的各个存储器单元，并且每次将这些存储器单元中的每一个与至少一个参考存储器单元进行比较，以便确定存储器单元的阈值是否低于 至少一个参考存储器单元; 确定其阈值高于所述至少一个参考小区的阈值的存储器单元的数量; 所述至少一个参考存储器单元被选择为具有逐渐更高的阈值; 当阈值高于给定参考阈值的存储单元的数量被发现足够低于设置在存储器件中的冗余存储单元的数量时，假定给定参考阈值为存储器件的较低参考阈值，则确定 存储单元阈值的统计分布。

公开(公告)号：US5982677A

公开(公告)日：1999-11-09

申请号：US163755

申请日：1998-09-30

申请人： Marco Fontana ,  Massimo Montanaro

发明人： Marco Fontana ,  Massimo Montanaro

IPC分类号： G05F3/26 ,  G11C5/14 ,  G11C16/30 ,  G11C7/00 ,  G05F3/16

CPC分类号： G11C16/30 ,  G05F3/262 ,  G11C5/147

摘要： A compensated voltage regulator of the type used in programming non-volatile memory cells of a memory cell matrix that is divided into sectors. The voltage regulator includes a comparator that is connected to a supply voltage. A first input terminal of the comparator is supplied a reference voltage, and a second input terminal is feedback connected to a program line. The control terminal of an output transistor is connected to an output terminal of the comparator, and a conduction terminal of the output transistor is connected to the memory cells by the program line. An output current is passed through a conduction terminal of the output transistor. Further, a compensation circuit is powered by the supply voltage. An input of the compensation circuit is connected to the output terminal of the comparator and to the output transistor, and an output of the compensation circuit is also connected to the output terminal of the comparator. This causes the duplication of a current that is suitably attenuated with respect to the output current and is useful in modifying the output voltage of the comparator.

摘要翻译： 一种用于编程划分为扇区的存储单元阵列的非易失性存储单元的类型的补偿电压调节器。 电压调节器包括连接到电源电压的比较器。 比较器的第一输入端被提供参考电压，第二输入端反馈连接到程序行。 输出晶体管的控制端子连接到比较器的输出端子，并且输出晶体管的导通端子通过编程线连接到存储器单元。 输出电流通过输出晶体管的导通端。 此外，补偿电路由电源电压供电。 补偿电路的输入连接到比较器的输出端和输出晶体管，补偿电路的输出也连接到比较器的输出端。 这导致相对于输出电流适当衰减的电流的复制，并且可用于修改比较器的输出电压。