公开(公告)号：US07818694B2

公开(公告)日：2010-10-19

申请号：US12342353

申请日：2008-12-23

申请人： Robert J Allen ,  Faye D Baker ,  Albert M Chu ,  Michael S Gray ,  Jason Hibbeler ,  Daniel N Maynard ,  Mervyn Y Tan ,  Robert F Walker

发明人： Robert J Allen ,  Faye D Baker ,  Albert M Chu ,  Michael S Gray ,  Jason Hibbeler ,  Daniel N Maynard ,  Mervyn Y Tan ,  Robert F Walker

IPC分类号： G06F17/50

CPC分类号： G06F17/5068

摘要： Optimizing an integrated circuit design to improve manufacturing yield using manufacturing data and algorithms to identify areas with high probability of failures, i.e. critical areas. The process further changes the layout of the circuit design to reduce critical area thereby reducing the probability of a fault occurring during manufacturing. Methods of identifying critical area include common run, geometry mapping, and Voronoi diagrams. Optimization includes but is not limited to incremental movement and adjustment of shape dimensions until optimization objectives are achieved and critical area is reduced.

摘要翻译： 使用制造数据和算法优化集成电路设计以提高制造产量，以识别故障概率高的区域，即关键区域。 该过程进一步改变电路设计的布局以减少临界面积，从而降低制造过程中发生故障的可能性。 确定关键区域的方法包括通用运行，几何映射和Voronoi图。 优化包括但不限于形状尺寸的增量移动和调整，直到达到优化目标并减小关键面积。

公开(公告)号：US06670283B2

公开(公告)日：2003-12-30

申请号：US09989389

申请日：2001-11-20

申请人： Faye D. Baker ,  Casey J. Grant ,  Mousa H. Ishaq ,  Joel M. Sharrow ,  James D. Weil

发明人： Faye D. Baker ,  Casey J. Grant ,  Mousa H. Ishaq ,  Joel M. Sharrow ,  James D. Weil

IPC分类号： H01L2131

CPC分类号： H01L21/02164 ,  H01L21/02115 ,  H01L21/0217 ,  H01L21/022 ,  H01L21/02271 ,  H01L21/02274 ,  H01L21/31612

摘要： Disclosed is a method of fabricating a semiconductor device, comprising: (a) providing a bare semiconductor substrate, the substrate having a frontside and a backside; (b) forming one or more protective films on the backside of the substrate; and (c) performing one or more wafer fabrication steps. Some or all the protective films may be removed and the method repeated multiple times during fabrication of the semiconductor device.

摘要翻译： 公开了一种制造半导体器件的方法，包括：（a）提供裸半导体衬底，所述衬底具有前侧和后侧; （b）在衬底的背面形成一个或多个保护膜; 和（c）执行一个或多个晶片制造步骤。 可以去除一些或全部保护膜，并且在制造半导体器件期间该方法重复多次。

公开(公告)号：US07823106B2

公开(公告)日：2010-10-26

申请号：US12045984

申请日：2008-03-11

申请人： Faye D. Baker ,  Mark R. Beckenbaugh ,  Jason J. Freerksen ,  Mark D. Levy

发明人： Faye D. Baker ,  Mark R. Beckenbaugh ,  Jason J. Freerksen ,  Mark D. Levy

IPC分类号： G06F17/50

CPC分类号： G06F17/5081 ,  G06F2217/12 ,  Y02P90/265

摘要： A method, computer system and program product introduce adding a variable performance ranking parameter to a diagram of a circuit to drive implementation of modifications that are yield improving, performance boosting, or performance-neutral. The information is paired to accomplish a more complete design for manufacturability modification in the design of circuits implemented on chips. In this matter, both yield and chip performance are improved.

摘要翻译： 一种方法，计算机系统和程序产品引入了将可变性能排名参数添加到电路图中，以驱动实现改进的效果，提高效率，提升性能或性能中立。 该信息配对，以便在芯片上实现的电路设计中完成更完整的可制造性修改设计。 在这个问题上，产量和芯片性能均有所提高。

公开(公告)号：US20090235214A1

公开(公告)日：2009-09-17

申请号：US12045984

申请日：2008-03-11

申请人： Faye D. Baker ,  Mark R. Beckenbaugh ,  Jason J. Freerksen ,  Mark D. Levy

发明人： Faye D. Baker ,  Mark R. Beckenbaugh ,  Jason J. Freerksen ,  Mark D. Levy

IPC分类号： G06F17/50

CPC分类号： G06F17/5081 ,  G06F2217/12 ,  Y02P90/265

摘要： A method, computer system and program product introduce adding a variable performance ranking parameter to a diagram of a circuit to drive implementation of modifications that are yield improving, performance boosting, or performance-neutral. The information is paired to accomplish a more complete design for manufacturability modification in the design of circuits implemented on chips. In this matter, both yield and chip performance are improved.

摘要翻译： 一种方法，计算机系统和程序产品引入了将可变性能排名参数添加到电路图中，以驱动实现改进的效果，提高效率，提升性能或性能中立。 该信息配对，以便在芯片上实现的电路设计中完成更完整的可制造性修改设计。 在这个问题上，产量和芯片性能均有所提高。

公开(公告)号：US20090100386A1

公开(公告)日：2009-04-16

申请号：US12342353

申请日：2008-12-23

申请人： Robert J. Allen ,  Faye D. Baker ,  Albert M. Chu ,  Michael S. Gray ,  Jason Hibbeler ,  Daniel N. Maynard ,  Mervyn Y. Tan ,  Robert F. Walker

发明人： Robert J. Allen ,  Faye D. Baker ,  Albert M. Chu ,  Michael S. Gray ,  Jason Hibbeler ,  Daniel N. Maynard ,  Mervyn Y. Tan ,  Robert F. Walker

IPC分类号： G06F17/50

CPC分类号： G06F17/5068

摘要： Optimizing an integrated circuit design to improve manufacturing yield using manufacturing data and algorithms to identify areas with high probability of failures, i.e. critical areas. The process further changes the layout of the circuit design to reduce critical area thereby reducing the probability of a fault occurring during manufacturing. Methods of identifying critical area include common run, geometry mapping, and Voronoi diagrams. Optimization includes but is not limited to incremental movement and adjustment of shape dimensions until optimization objectives are achieved and critical area is reduced.

摘要翻译： 使用制造数据和算法优化集成电路设计以提高制造产量，以识别故障概率高的区域，即关键区域。 该过程进一步改变电路设计的布局以减少临界面积，从而降低制造过程中发生故障的可能性。 确定关键区域的方法包括通用运行，几何映射和Voronoi图。 优化包括但不限于形状尺寸的增量移动和调整，直到达到优化目标并减小关键面积。

公开(公告)号：US06232639B1

公开(公告)日：2001-05-15

申请号：US09107900

申请日：1998-06-30

申请人： Faye D. Baker ,  Jeffrey S. Brown ,  Robert J. Gauthier, Jr. ,  Steven J. Holmes ,  Robert K. Leidy ,  Edward J. Nowak ,  Steven H. Voldman

发明人： Faye D. Baker ,  Jeffrey S. Brown ,  Robert J. Gauthier, Jr. ,  Steven J. Holmes ,  Robert K. Leidy ,  Edward J. Nowak ,  Steven H. Voldman

IPC分类号： H01L2976

CPC分类号： H01L21/823878 ,  H01L27/0921 ,  Y10S148/137

摘要： The preferred embodiment of the present invention overcomes the limitations of the prior art and provides a device and method to increase the latch-up immunity of CMOS devices by forming implants at the well edges. The preferred method uses hybrid resist to form these implants at the edges of the N-wells and/or P-wells. The implants reduce the lifetime of minority carriers in the parasitic transistor, and hence reduce the gain of the parasitic transistor. This reduces the propensity of the CMOS device to latch-up. The preferred embodiment method allows these implants to be formed without requiring additional masking steps over prior art methods. Furthermore, the preferred method for forming the implants results in implants that are self aligned to the edges of the wells.

摘要翻译： 本发明的优选实施例克服了现有技术的限制，并且提供了一种通过在阱边缘处形成植入物来增加CMOS器件的闩锁抗扰度的装置和方法。 优选的方法使用混合抗蚀剂在N阱和/或P阱的边缘形成这些植入物。 植入物减少了寄生晶体管中少数载流子的寿命，从而降低了寄生晶体管的增益。 这降低了CMOS器件闭锁的倾向。 优选实施例方法允许形成这些植入物，而不需要比现有技术方法更多的掩蔽步骤。 此外，用于形成植入物的优选方法导致与孔的边缘自对准的植入物。

公开(公告)号：US6033949A

公开(公告)日：2000-03-07

申请号：US107813

申请日：1998-06-30

申请人： Faye D. Baker ,  Jeffrey S. Brown ,  Robert J. Gauthier, Jr. ,  Steven J. Holmes ,  Robert K. Leidy ,  Edward J. Nowak ,  Steven H. Voldman

发明人： Faye D. Baker ,  Jeffrey S. Brown ,  Robert J. Gauthier, Jr. ,  Steven J. Holmes ,  Robert K. Leidy ,  Edward J. Nowak ,  Steven H. Voldman

IPC分类号： H01L21/761 ,  G03F7/004 ,  H01L21/8238 ,  H01L27/08 ,  H01L27/092

CPC分类号： H01L21/823878 ,  H01L27/0921 ,  Y10S148/137

摘要： The preferred embodiment of the present invention overcomes the limitations of the prior art and provides a device and method to increase the latch-up immunity of CMOS devices by forming implants at the well edges. The preferred method uses hybrid resist to form these implants at the edges of the N-wells and/or P-wells. The implants reduce the lifetime of minority carriers in the parasitic transistor, and hence reduce the gain of the parasitic transistor. This reduces the propensity of the CMOS device to latch-up. The preferred embodiment method allows these implants to be formed without requiring additional masking steps over prior art methods. Furthermore, the preferred method for forming the implants results in implants that are self aligned to the edges of the wells.

摘要翻译： 本发明的优选实施例克服了现有技术的限制，并且提供了一种通过在阱边缘处形成植入物来增加CMOS器件的闩锁抗扰度的装置和方法。 优选的方法使用混合抗蚀剂在N阱和/或P阱的边缘形成这些植入物。 植入物减少了寄生晶体管中少数载流子的寿命，从而降低了寄生晶体管的增益。 这降低了CMOS器件闭锁的倾向。 优选实施例方法允许形成这些植入物，而不需要比现有技术方法更多的掩蔽步骤。 此外，用于形成植入物的优选方法导致与孔的边缘自对准的植入物。

公开(公告)号：US20070294648A1

公开(公告)日：2007-12-20

申请号：US11424922

申请日：2006-06-19

申请人： Robert J. Allen ,  Faye D. Baker ,  Albert M. Chu ,  Michael S. Gray ,  Jason Hibbeler ,  Daniel N. Maynard ,  Mervyn Y. Tan ,  Robert F. Walker

发明人： Robert J. Allen ,  Faye D. Baker ,  Albert M. Chu ,  Michael S. Gray ,  Jason Hibbeler ,  Daniel N. Maynard ,  Mervyn Y. Tan ,  Robert F. Walker

IPC分类号： G06F17/50

CPC分类号： G06F17/5068

摘要： A method of and service for optimizing an integrated circuit design to improve manufacturing yield. The invention uses manufacturing data and algorithms to identify areas with high probability of failures, i.e. critical areas. The invention further changes the layout of the circuit design to reduce critical area thereby reducing the probability of a fault occurring during manufacturing. Methods of identifying critical area include common run, geometry mapping, and Voronoi diagrams. Optimization includes but is not limited to incremental movement and adjustment of shape dimensions until optimization objectives are achieved and critical area is reduced.

摘要翻译： 一种用于优化集成电路设计以提高制造产量的方法和服务。 本发明使用制造数据和算法来识别故障概率高的区域，即关键区域。 本发明进一步改变电路设计的布局以减少临界面积，从而降低在制造过程中发生故障的可能性。 确定关键区域的方法包括通用运行，几何映射和Voronoi图。 优化包括但不限于形状尺寸的增量移动和调整，直到达到优化目标并减小关键面积。

公开(公告)号：US07503020B2

公开(公告)日：2009-03-10

申请号：US11424922

申请日：2006-06-19

申请人： Robert J. Allen ,  Faye D. Baker ,  Albert M. Chu ,  Michael S. Gray ,  Jason Hibbeler ,  Daniel N. Maynard ,  Mervyn Y. Tan ,  Robert F. Walker

发明人： Robert J. Allen ,  Faye D. Baker ,  Albert M. Chu ,  Michael S. Gray ,  Jason Hibbeler ,  Daniel N. Maynard ,  Mervyn Y. Tan ,  Robert F. Walker

IPC分类号： G06F17/50

CPC分类号： G06F17/5068

摘要： A method of and service for optimizing an integrated circuit design to improve manufacturing yield. The invention uses manufacturing data and algorithms to identify areas with high probability of failures, i.e. critical areas. The invention further changes the layout of the circuit design to reduce critical area thereby reducing the probability of a fault occurring during manufacturing. Methods of identifying critical area include common run, geometry mapping, and Voronoi diagrams. Optimization includes but is not limited to incremental movement and adjustment of shape dimensions until optimization objectives are achieved and critical area is reduced.

摘要翻译： 一种用于优化集成电路设计以提高制造产量的方法和服务。 本发明使用制造数据和算法来识别故障概率高的区域，即关键区域。 本发明进一步改变电路设计的布局以减少临界面积，从而降低在制造过程中发生故障的可能性。 确定关键区域的方法包括通用运行，几何映射和Voronoi图。 优化包括但不限于形状尺寸的增量移动和调整，直到达到优化目标并减小关键面积。

公开(公告)号：US5861330A

公开(公告)日：1999-01-19

申请号：US852466

申请日：1997-05-07

申请人： Faye D. Baker ,  Jeffrey S. Brown ,  Robert J. Gauthier, Jr. ,  Steven J. Holmes ,  Robert K. Leidy ,  Edward J. Nowak ,  Steven H. Voldman

发明人： Faye D. Baker ,  Jeffrey S. Brown ,  Robert J. Gauthier, Jr. ,  Steven J. Holmes ,  Robert K. Leidy ,  Edward J. Nowak ,  Steven H. Voldman

IPC分类号： H01L21/761 ,  G03F7/004 ,  H01L21/8238 ,  H01L27/08 ,  H01L27/092

CPC分类号： H01L21/823878 ,  H01L27/0921 ,  Y10S148/137

摘要： The preferred embodiment of the present invention overcomes the limitations of the prior art and provides a device and method to increase the latch-up immunity of CMOS devices by forming implants at the well edges. The preferred method uses hybrid resist to form these implants at the edges of the N-wells and/or P-wells. The implants reduce the lifetime of minority carriers in the parasitic transistor, and hence reduce the gain of the parasitic transistor. This reduces the propensity of the CMOS device to latch-up. The preferred embodiment method allows these implants to be formed without requiring additional masking steps over prior art methods. Furthermore, the preferred method for forming the implants results in implants that are self aligned to the edges of the wells.