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    CRITICAL AREA COMPUTATION OF COMPOSITE FAULT MECHANISMS USING VORONOI DIAGRAMS
    4.
    发明申请
    CRITICAL AREA COMPUTATION OF COMPOSITE FAULT MECHANISMS USING VORONOI DIAGRAMS 失效
    使用VORONOI图形的复合故障机制的关键区域计算

    公开(公告)号：US20080235641A1

    公开(公告)日：2008-09-25

    申请号：US12132714

    申请日：2008-06-04

    申请人： Robert J. Allen ,  Evanthia Papadopoulou ,  Mervyn Yee-Min Tan

    发明人： Robert J. Allen ,  Evanthia Papadopoulou ,  Mervyn Yee-Min Tan

    IPC分类号： G06F17/50

    CPC分类号： G06F17/5068

    摘要： Disclosed is a method that determines critical areas associated with different types of fault mechanisms in an integrated circuit design. The invention does this by constructing individual Voronoi diagrams for critical areas of individual fault mechanisms and a composite Voronoi diagram based on the individual Voronoi diagrams. The invention computes the critical area for composite fault mechanisms of the integrated circuit design based on the composite Voronoi diagram.

    摘要翻译： 公开了一种在集成电路设计中确定与不同类型的故障机制相关联的关键区域的方法。 本发明通过为单个故障机制的关键区域构建单独的Voronoi图和基于各个Voronoi图的复合Voronoi图来实现。 本发明基于复合Voronoi图计算了集成电路设计复合故障机理的关键区域。

    Critical area computation of composite fault mechanisms using Voronoi diagrams
    5.
    发明授权
    Critical area computation of composite fault mechanisms using Voronoi diagrams 有权
    使用Voronoi图的复合故障机制的关键区域计算

    公开(公告)号：US07404159B2

    公开(公告)日：2008-07-22

    申请号：US11538913

    申请日：2006-10-05

    申请人： Robert J. Allen ,  Evanthia Papadopoulou ,  Mervyn Yee-Min Tan

    发明人： Robert J. Allen ,  Evanthia Papadopoulou ,  Mervyn Yee-Min Tan

    IPC分类号： G06F17/50

    CPC分类号： G06F17/5068

    摘要： Disclosed is a method that determines critical areas associated with different types of fault mechanisms in an integrated circuit design. The invention does this by constructing individual Voronoi diagrams for critical areas of individual fault mechanisms and a composite Voronoi diagram based on the individual Voronoi diagrams. The invention computes the critical area for composite fault mechanisms of the integrated circuit design based on the composite Voronoi diagram.

    摘要翻译： 公开了一种在集成电路设计中确定与不同类型的故障机制相关联的关键区域的方法。 本发明通过为单个故障机制的关键区域构建单独的Voronoi图和基于各个Voronoi图的复合Voronoi图来实现。 本发明基于复合Voronoi图计算了集成电路设计复合故障机理的关键区域。

    Critical area computation of composite fault mechanisms using voronoi diagrams
    6.
    发明授权
    Critical area computation of composite fault mechanisms using voronoi diagrams 有权
    使用voronoi图的复合故障机制的关键区域计算

    公开(公告)号：US07143371B2

    公开(公告)日：2006-11-28

    申请号：US10709293

    申请日：2004-04-27

    申请人： Robert J. Allen ,  Evanthia Papadopoulou ,  Mervyn Yee-Min Tan

    发明人： Robert J. Allen ,  Evanthia Papadopoulou ,  Mervyn Yee-Min Tan

    IPC分类号： G06F17/50

    CPC分类号： G06F17/5068

    摘要： Disclosed is a method that determines critical areas associated with different types of fault mechanisms in an integrated circuit design. The invention does this by constructing individual Voronoi diagrams for critical areas of individual fault mechanisms and a composite Voronoi diagram based on the individual Voronoi diagrams. The invention computes the critical area for composite fault mechanisms of the integrated circuit design based on the composite Voronoi diagram.

    摘要翻译： 公开了一种在集成电路设计中确定与不同类型的故障机制相关联的关键区域的方法。 本发明通过为单个故障机制的关键区域构建单独的Voronoi图和基于各个Voronoi图的复合Voronoi图来实现。 本发明基于复合Voronoi图计算了集成电路设计复合故障机理的关键区域。

    Content based yield prediction of VLSI designs
    7.
    发明授权
    Content based yield prediction of VLSI designs 失效
    基于内容的VLSI设计的产量预测

    公开(公告)号：US07661081B2

    公开(公告)日：2010-02-09

    申请号：US12101599

    申请日：2008-04-11

    申请人： Robert J. Allen ,  Daria R. Dooling ,  Jason D. Hibbeler ,  Daniel N. Maynard ,  Sarah C. Prue ,  Ralph J. Williams

    发明人： Robert J. Allen ,  Daria R. Dooling ,  Jason D. Hibbeler ,  Daniel N. Maynard ,  Sarah C. Prue ,  Ralph J. Williams

    IPC分类号： G06F17/50

    CPC分类号： G06F17/5045

    摘要： An integrated circuit system and program product for predicting yield of a VLSI design. An integrated circuit system is provided including a system for identifying and grouping sub-circuits contained within an integrated circuit design by circuit type; a critical area calculation system for determining critical area values for different regions, wherein each different region is associated with a circuit type; a tallying system for calculating a plurality of tallies of critical area values based on circuit type; and a plurality of modeling subsystems for separately modeling each of the plurality of tallies based on circuit type.

    摘要翻译： 一种用于预测VLSI设计产量的集成电路系统和程序产品。 提供一种集成电路系统，包括用于通过电路类型识别和集成集成电路设计中所包含的子电路的系统; 用于确定不同区域的临界面积值的关键区域计算系统，其中每个不同区域与电路类型相关联; 用于基于电路类型计算多个临界面积值的计数系统; 以及多个建模子系统，用于基于电路类型对所述多个提议中的每一个进行单独建模。

    CONTENT BASED YIELD PREDICTION OF VLSI DESIGNS
    8.
    发明申请
    CONTENT BASED YIELD PREDICTION OF VLSI DESIGNS 失效
    基于内容的VLSI设计预测

    公开(公告)号：US20080195989A1

    公开(公告)日：2008-08-14

    申请号：US12101599

    申请日：2008-04-11

    申请人： Robert J. Allen ,  Daria R. Dooling ,  Jason D. Hibbeler ,  Daniel N. Maynard ,  Sarah C. Prue ,  Ralph J. Williams

    发明人： Robert J. Allen ,  Daria R. Dooling ,  Jason D. Hibbeler ,  Daniel N. Maynard ,  Sarah C. Prue ,  Ralph J. Williams

    IPC分类号： G06F9/45

    CPC分类号： G06F17/5045

    摘要： An integrated circuit and program product for predicting yield of a VLSI design. An integrated circuit is provided including a system for identifying and grouping sub-circuits contained within an integrated circuit design by circuit type; a critical area calculation system for determining critical area values for different regions, wherein each different region is associated with a circuit type; a tallying system for calculating a plurality of tallies of critical area values based on circuit type; and a plurality of modeling subsystems for separately modeling each of the plurality of tallies based on circuit type.

    摘要翻译： 一种用于预测VLSI设计产量的集成电路和程序产品。 提供一种集成电路，包括用于通过电路类型识别和分组集成电路设计中包含的子电路的系统; 用于确定不同区域的临界面积值的关键区域计算系统，其中每个不同区域与电路类型相关联; 用于基于电路类型计算多个临界面积值的计数系统; 以及多个建模子系统，用于基于电路类型对所述多个提议中的每一个进行单独建模。

    Content based yield prediction of VLSI designs
    9.
    发明授权
    Content based yield prediction of VLSI designs 有权
    基于内容的VLSI设计的产量预测

    公开(公告)号：US07389480B2

    公开(公告)日：2008-06-17

    申请号：US10908342

    申请日：2005-05-09

    申请人： Robert J. Allen ,  Daria R. Dooling ,  Jason D. Hibbeler ,  Daniel N. Maynard ,  Sarah C. Prue ,  Ralph J. Williams

    发明人： Robert J. Allen ,  Daria R. Dooling ,  Jason D. Hibbeler ,  Daniel N. Maynard ,  Sarah C. Prue ,  Ralph J. Williams

    IPC分类号： G06F17/50

    CPC分类号： G06F17/5045

    摘要： A system, method and program product for predicting yield of a VLSI design. A method is provided including the steps of: identifying and grouping sub-circuits contained within an integrated circuit design by type; calculating critical area values for regions within the integrated circuit design; and applying different yield models to critical area values based on the types of the regions used to calculate the critical area values, wherein each yield model is dependent on a type.

    摘要翻译： 一种用于预测VLSI设计产量的系统，方法和程序产品。 提供了一种方法，包括以下步骤：通过类型识别和分组集成电路设计中包含的子电路; 计算集成电路设计中区域的关键面积值; 以及基于用于计算临界面积值的区域的类型将不同的屈服模型应用于临界区域值，其中每个产量模型依赖于类型。

    IC layout optimization to improve yield
    10.
    发明授权
    IC layout optimization to improve yield 失效
    IC布局优化提高产量

    公开(公告)号：US07503020B2

    公开(公告)日：2009-03-10

    申请号：US11424922

    申请日：2006-06-19

    申请人： Robert J. Allen ,  Faye D. Baker ,  Albert M. Chu ,  Michael S. Gray ,  Jason Hibbeler ,  Daniel N. Maynard ,  Mervyn Y. Tan ,  Robert F. Walker

    发明人： Robert J. Allen ,  Faye D. Baker ,  Albert M. Chu ,  Michael S. Gray ,  Jason Hibbeler ,  Daniel N. Maynard ,  Mervyn Y. Tan ,  Robert F. Walker

    IPC分类号： G06F17/50

    CPC分类号： G06F17/5068

    摘要： A method of and service for optimizing an integrated circuit design to improve manufacturing yield. The invention uses manufacturing data and algorithms to identify areas with high probability of failures, i.e. critical areas. The invention further changes the layout of the circuit design to reduce critical area thereby reducing the probability of a fault occurring during manufacturing. Methods of identifying critical area include common run, geometry mapping, and Voronoi diagrams. Optimization includes but is not limited to incremental movement and adjustment of shape dimensions until optimization objectives are achieved and critical area is reduced.

    摘要翻译： 一种用于优化集成电路设计以提高制造产量的方法和服务。 本发明使用制造数据和算法来识别故障概率高的区域，即关键区域。 本发明进一步改变电路设计的布局以减少临界面积，从而降低在制造过程中发生故障的可能性。 确定关键区域的方法包括通用运行，几何映射和Voronoi图。 优化包括但不限于形状尺寸的增量移动和调整，直到达到优化目标并减小关键面积。