公开(公告)号：US5364144A

公开(公告)日：1994-11-15

申请号：US186832

申请日：1994-01-25

申请人： Michael J. Satterfield ,  Theodore C. Caramberis ,  Glenn T. Tharp

发明人： Michael J. Satterfield ,  Theodore C. Caramberis ,  Glenn T. Tharp

IPC分类号： H01L21/673 ,  B65D25/28

CPC分类号： H01L21/67326 ,  H01L21/68707

摘要： Embodiments of the present invention include a cassette transporting apparatus having 1) a first fork member 31 and a second fork member 31, wherein each fork member 31 has a shaft 62 and a tab 63; 2) a first member 31 and a second fork member 31, wherein each fork member 31 includes a shaft 62 having a distal section 42 that is beveled; or 3) a curved handle 33. In one embodiment, the cassette transporting apparatus is a cassette fork 20 for manually transporting a cassette and includes a locking tab 63, the beveled distal section 42, and the curved handle 33. In another embodiment, the cassette transporting apparatus is a mechanical cassette transporting system 100 including an elevator 101 and the fork members 31. The design of the fork members 31 is cassette specific rather than both cassette and apparatus specific.

摘要翻译： 本发明的实施例包括具有1）第一叉构件31和第二叉构件31的盒输送装置，其中每个叉构件31具有轴62和突片63; 2）第一构件31和第二叉构件31，其中每个叉构件31包括具有倾斜的远侧段42的轴62; 或者3）弯曲手柄33.在一个实施例中，盒输送装置是用于手动输送盒的盒式叉20，包括锁定片63，斜面远端部分42和弯曲手柄33.在另一个实施例中， 盒式输送装置是包括升降机101和叉构件31的机械盒式输送系统100.叉构件31的设计是盒特定的，而不是盒和装置特有的。

公开(公告)号：US06649541B1

公开(公告)日：2003-11-18

申请号：US09920490

申请日：2001-08-01

申请人： Allen Lewis Evans ,  David E. Brown ,  Michael J. Satterfield ,  Arturo N. Morosoff

发明人： Allen Lewis Evans ,  David E. Brown ,  Michael J. Satterfield ,  Arturo N. Morosoff

IPC分类号： H01L21469

CPC分类号： H01L21/02274 ,  C23C16/402 ,  H01L21/02164 ,  H01L21/02211 ,  H01L21/31612 ,  H01L21/76801 ,  H01L21/76829

摘要： The method disclosed herein provides a semiconducting substrate, positioning the substrate in a high density plasma process chamber, and forming a layer of silicon-rich silicon dioxide above the substrate using a high density plasma process with an oxygen/silane flowrate ratio that is less than or equal to 0.625. In another embodiment, the method provides a semiconducting substrate having a partially formed integrated circuit device formed thereabove, the integrated circuit device having a plurality of conductive interconnections, e.g., conductive lines or conductive plugs, formed thereon, and positioning the substrate in a high density plasma process chamber. The method further includes forming a first layer of silicon dioxide between the plurality of conductive interconnections using a high density plasma process with an oxygen/silane flowrate ratio less than 1.0, and forming a layer of insulating material above the first layer between the conductive interconnections. In another aspect of the present invention, an integrated circuit device has of a plurality of conductive interconnections, e.g., conductive lines, formed above a semiconducting substrate, a layer of silicon dioxide having a silicon content ranging from approximately 50-75 weight percent positioned between the conductive inter-connections, and a layer of insulating material positioned above the layer of silicon dioxide between the conductive interconnections.

摘要翻译： 本文公开的方法提供半导体衬底，将衬底定位在高密度等离子体处理室中，并且使用氧/硅烷流量比小于等于的高密度等离子体工艺在衬底上形成富硅二氧化硅层 或等于0.625。 在另一个实施例中，该方法提供了一种半导体衬底，其具有形成在其上面的部分形成的集成电路器件，该集成电路器件具有多个导电互连，例如在其上形成的导电线或导电插塞，并且将衬底以高密度 等离子体处理室。 该方法还包括使用氧/硅烷流量比小于1.0的高密度等离子体工艺在多个导电互连之间形成第二层二氧化硅，以及在导电互连之间在第一层之上形成一层绝缘材料。 在本发明的另一方面，集成电路器件具有形成在半导体衬底上方的多个导电互连（例如，导线），二氧化硅层的硅含量范围为约50-75重量％ 导电互连，以及位于导电互连之间的二氧化硅层之上的绝缘材料层。

公开(公告)号：US06524869B1

公开(公告)日：2003-02-25

申请号：US09780178

申请日：2001-02-09

申请人： Michael J. Satterfield ,  Laura A. Pressley ,  Terri A. Couteau ,  Daniel E. Sutton ,  Bryon K. Hance ,  David Hendrix

发明人： Michael J. Satterfield ,  Laura A. Pressley ,  Terri A. Couteau ,  Daniel E. Sutton ,  Bryon K. Hance ,  David Hendrix

IPC分类号： H01L2166

CPC分类号： H01L22/12

摘要： Various methods and apparatus are provided for testing an ion implantation tool. In one aspect, a method of testing an ion implanter is provided that includes forming a mask with a preselected pattern on a substrate. An ion implant is performed on the mask with the ion implanter. Following the ion implant, a scan of the mask is performed to identify any defects thereon. Defects appearing on the mask following the implant are indicative of latent mechanisms at work within the implanter. Ion implanter induced defects may be economically analyzed.

摘要翻译： 提供了用于测试离子注入工具的各种方法和装置。 一方面，提供了一种测试离子注入机的方法，其包括在衬底上形成具有预选图案的掩模。 用离子注入机在掩模上进行离子注入。 在离子注入之后，执行掩模的扫描以识别其上的任何缺陷。 在植入物之后出现在掩模上的缺陷表示在注入机内工作的潜在机制。 离子注入机诱导的缺陷可能经济分析。

公开(公告)号：US06566886B1

公开(公告)日：2003-05-20

申请号：US09819785

申请日：2001-03-28

申请人： Terri A. Couteau ,  Michael J. Satterfield ,  Laura A. Pressley

发明人： Terri A. Couteau ,  Michael J. Satterfield ,  Laura A. Pressley

IPC分类号： G01R3108

CPC分类号： G01N29/28 ,  G01N29/12 ,  G01N29/348 ,  G01N2291/02433 ,  G01N2291/2698

摘要： Various methods of inspecting circuit structures are provided. In one aspect, a method of detecting structural defects in a circuit structure is provided. A natural frequency of the circuit structure is determined and the circuit structure is immersed in a liquid. A first plurality of sonic pulses is sent through the liquid. The first plurality of sonic pulses have a first frequency range selected to produce a plurality of collapsing bubbles proximate the circuit structure. The collapsing bubbles produce a second plurality of sonic pulses that have a second frequency range near or including the natural frequency of the circuit structure whereby the second plurality of sonic pulses causes the circuit structure to resonate. Thereafter, the circuit structure is inspected for structural damage. Early identification of crystalline defects is facilitated.

摘要翻译： 提供了检查电路结构的各种方法。 一方面，提供一种检测电路结构中的结构缺陷的方法。 确定电路结构的固有频率，并将电路结构浸入液体中。 通过液体发送第一组多个声波脉冲。 第一组多个声波脉冲具有选择的第一频率范围以在电路结构附近产生多个塌陷气泡。 塌陷气泡产生第二多个声波脉冲，其具有靠近或包括电路结构的固有频率的第二频率范围，由此第二多个声波脉冲导致电路结构谐振。 此后，检查电路结构是否有结构损坏。 有利于早期鉴定晶体缺陷。