公开(公告)号：US06524869B1

公开(公告)日：2003-02-25

申请号：US09780178

申请日：2001-02-09

申请人： Michael J. Satterfield ,  Laura A. Pressley ,  Terri A. Couteau ,  Daniel E. Sutton ,  Bryon K. Hance ,  David Hendrix

发明人： Michael J. Satterfield ,  Laura A. Pressley ,  Terri A. Couteau ,  Daniel E. Sutton ,  Bryon K. Hance ,  David Hendrix

IPC分类号： H01L2166

CPC分类号： H01L22/12

摘要： Various methods and apparatus are provided for testing an ion implantation tool. In one aspect, a method of testing an ion implanter is provided that includes forming a mask with a preselected pattern on a substrate. An ion implant is performed on the mask with the ion implanter. Following the ion implant, a scan of the mask is performed to identify any defects thereon. Defects appearing on the mask following the implant are indicative of latent mechanisms at work within the implanter. Ion implanter induced defects may be economically analyzed.

摘要翻译： 提供了用于测试离子注入工具的各种方法和装置。 一方面，提供了一种测试离子注入机的方法，其包括在衬底上形成具有预选图案的掩模。 用离子注入机在掩模上进行离子注入。 在离子注入之后，执行掩模的扫描以识别其上的任何缺陷。 在植入物之后出现在掩模上的缺陷表示在注入机内工作的潜在机制。 离子注入机诱导的缺陷可能经济分析。

公开(公告)号：US06348289B1

公开(公告)日：2002-02-19

申请号：US09366486

申请日：1999-08-03

申请人： Terri A. Couteau ,  W. Jarrett Campbell ,  Anthony Toprac

发明人： Terri A. Couteau ,  W. Jarrett Campbell ,  Anthony Toprac

IPC分类号： G03F730

CPC分类号： H01L22/20 ,  B25J9/1664 ,  G05B2219/45065 ,  H01L21/28123 ,  H01L21/32134

摘要： A method for processing a semiconductor topography is presented. In the present processing method, a semiconductor topography may be provided having a polysilicon feature arranged above a semiconductor substrate. The polysilicon feature may have an initial polysilicon feature critical dimension (CD). A chemical mixture, preferably contained in a chemical vessel, may also be provided. A polysilicon etch rate-effective attribute of the chemical mixture may be measured. Subsequently, an exposure time to the chemical mixture for the semiconductor topography may be calculated from the polysilicon etch rate-effective attribute, the initial polysilicon feature CD, and a goal polysilicon feature CD. By calculating an exposure time for the semiconductor topography in such a manner, the method preferably allows a final polysilicon feature CD to be more accurately controlled than in conventional processes.

摘要翻译： 提出了一种半导体形貌的处理方法。 在本处理方法中，可以提供具有布置在半导体衬底之上的多晶硅特征的半导体形貌。 多晶硅特征可以具有初始多晶硅特征临界尺寸（CD）。 还可以提供优选包含在化学容器中的化学混合物。 可以测量化学混合物的多晶硅蚀刻速率有效属性。 随后，可以从多晶硅蚀刻速率有效属性，初始多晶硅特征CD和目标多晶硅特征CD计算到用于半导体形貌的化学混合物的曝光时间。 通过以这种方式计算半导体形貌的曝光时间，该方法优选地允许比常规工艺更精确地控制最终多晶硅特征CD。

公开(公告)号：US06326313B1

公开(公告)日：2001-12-04

申请号：US09295941

申请日：1999-04-21

申请人： Terri A. Couteau ,  Stacie Y. Brown

发明人： Terri A. Couteau ,  Stacie Y. Brown

IPC分类号： H01L21302

CPC分类号： H01L21/67086 ,  H01L21/31111

摘要： A method of performing a nitride strip process step for a plurality of semiconductor wafers includes partially draining the chemical solution within a chemical bath after every nitride strip in which the oxide etch rate is within a specified range. If the oxide etch rate is above the specified range, the partial drain is performed. Once the etch rate falls within the range, the partial drain is performed every time a bath increment signal is received. If the etch rate falls below the specified range, then the bath is completely drained so that the solution may be replaced with fresh chemicals. While it is generally desirable to minimize the amount of field oxide that is removed during the nitride strip process step, the field oxide etch should be maintained at a specified level because, when below that level, the chemical solution silicon content is too high risking the possibility that the silicon will precipitate and cause undesirable effects including coating the wafers being stripped of nitride. The partial drain time is adjusted from a nominal rate according to measured oxide etch rates. For a first bath in a sequential series of baths, the nominal partial drain time is fifteen seconds. For a second bath in the sequential series of baths, the nominal rate is ten seconds.

摘要翻译： 对于多个半导体晶片执行氮化物带处理步骤的方法包括在其中氧化物蚀刻速率在特定范围内的每个氮化物条之后，在化学浴中部分地排出化学溶液。 如果氧化物蚀刻速率高于指定范围，则执行部分漏极。 一旦蚀刻速率落在该范围内，则每次接收到浴增量信号时都执行部分漏极。 如果蚀刻速率低于指定范围，则浴液被完全排出，以便溶液可以用新鲜的化学品代替。 虽然通常希望使在氮化物带材工艺步骤期间去除的场氧化物的量最小化，但是场氧化物蚀刻应当保持在指定的水平，因为当低于该水平时，化学溶液的硅含量太高， 硅会沉淀并引起不希望有的影响，包括涂覆晶片被剥离氮化物的可能性。 根据测量的氧化物蚀刻速率，从标称速率调节局部放电时间。 对于连续浴缸中的第一浴，标称部分排水时间为15秒。 对于连续浴中的第二浴，标称速率为10秒。

公开(公告)号：US06492275B2

公开(公告)日：2002-12-10

申请号：US09488870

申请日：2000-01-21

申请人： Deborah J. Riley ,  Terri A. Couteau

发明人： Deborah J. Riley ,  Terri A. Couteau

IPC分类号： H01L21311

CPC分类号： H01L29/6659 ,  H01L21/31111

摘要： Methods of patterning sidewall spacers are provided. In one aspect, a method of fabricating a circuit device includes forming a gate on a substrate and forming a first oxide spacer and a second oxide spacer adjacent to the gate. The width of the gate and the first and second oxide spacers is measured. The widths of the first and second oxide spacers are trimmed if the width of the gate and the first and second oxide spacers exceeds a preselected maximum value by exposing the first and second oxide spacers to a solution of ammonium hydroxide, hydrogen peroxide and water for a preselected like and rinsing with deionized water. Spacer width may be finely tuned to reduce the risk of weak overlap and to improve device characteristics through shorter channels.

摘要翻译： 提供图案化侧壁间隔物的方法。 一方面，一种制造电路器件的方法包括在衬底上形成栅极，并形成邻近栅极的第一氧化物间隔物和第二氧化物间隔物。 测量栅极和第一和第二氧化物间隔物的宽度。 如果通过将第一和第二氧化物间隔物暴露于氢氧化铵，过氧化氢和水的溶液中，如果栅极和第一和第二氧化物间隔物的宽度超过预选的最大值，则第一和第二氧化物间隔物的宽度被修整 预先选择和用去离子水冲洗。 间隔宽度可以被微调，以减少弱重叠的风险，并通过较短的通道改善设备特性。

公开(公告)号：US06790683B1

公开(公告)日：2004-09-14

申请号：US10303224

申请日：2002-11-25

申请人： Richard J. Markle ,  Terri A. Couteau

发明人： Richard J. Markle ,  Terri A. Couteau

IPC分类号： H01L2100

CPC分类号： H01L21/67253 ,  G01N21/47 ,  H01L21/67086 ,  H01L22/20

摘要： The present invention is generally directed to various methods of controlling wet chemical processes in forming metal silicide regions, and a system for performing same. In one illustrative embodiment, the method comprises providing a substrate having a layer of unreacted refractory metal and at least one metal silicide region formed thereabove, performing a wet chemical process to remove at least a portion of the layer of unreacted refractory metal, measuring at least one characteristic of the portion of the layer of unreacted refractory metal while the wet chemical process is being performed, and controlling at least one parameter of the wet chemical process based upon the measured at least one characteristic of the portion of the layer of unreacted refractory metal. In another illustrative embodiment, the method comprises providing a substrate having a layer of unreacted refractory metal and at least one metal silicide region formed thereabove, performing a wet chemical process to remove at least a portion of the layer of unreacted refractory metal, measuring at least one characteristic of the portion of the layer of unreacted refractory metal after at least some of the wet chemical process has been performed, and controlling at least one parameter of the wet chemical process based upon the measured at least one characteristic of the portion of the layer of unreacted refractory metal.

摘要翻译： 本发明一般涉及在形成金属硅化物区域中控制湿化学工艺的各种方法，以及用于执行其的系统。 在一个说明性实施例中，该方法包括提供具有未反应的难熔金属层和形成于其上的至少一个金属硅化物区域的基底，执行湿化学工艺以去除至少一部分未反应的难熔金属层，至少测量 在进行湿化学处理时，未反应的难熔金属层的一部分的一个特征，并且基于所测量的未反应的难熔金属层的该部分的至少一个特征来控制湿化学工艺的至少一个参数 。 在另一说明性实施例中，该方法包括提供具有未反应的难熔金属层和形成在其上方的至少一个金属硅化物区域的基底，执行湿化学工艺以去除至少一部分未反应的难熔金属层，至少测量 在进行了至少一些湿化学处理之后，未反应的难熔金属层的该部分的一个特征是基于所测定的层的该部分的至少一个特性来控制湿化学工艺的至少一个参数 的未反应的难熔金属。

公开(公告)号：US06566886B1

公开(公告)日：2003-05-20

申请号：US09819785

申请日：2001-03-28

申请人： Terri A. Couteau ,  Michael J. Satterfield ,  Laura A. Pressley

发明人： Terri A. Couteau ,  Michael J. Satterfield ,  Laura A. Pressley

IPC分类号： G01R3108

CPC分类号： G01N29/28 ,  G01N29/12 ,  G01N29/348 ,  G01N2291/02433 ,  G01N2291/2698

摘要： Various methods of inspecting circuit structures are provided. In one aspect, a method of detecting structural defects in a circuit structure is provided. A natural frequency of the circuit structure is determined and the circuit structure is immersed in a liquid. A first plurality of sonic pulses is sent through the liquid. The first plurality of sonic pulses have a first frequency range selected to produce a plurality of collapsing bubbles proximate the circuit structure. The collapsing bubbles produce a second plurality of sonic pulses that have a second frequency range near or including the natural frequency of the circuit structure whereby the second plurality of sonic pulses causes the circuit structure to resonate. Thereafter, the circuit structure is inspected for structural damage. Early identification of crystalline defects is facilitated.

摘要翻译： 提供了检查电路结构的各种方法。 一方面，提供一种检测电路结构中的结构缺陷的方法。 确定电路结构的固有频率，并将电路结构浸入液体中。 通过液体发送第一组多个声波脉冲。 第一组多个声波脉冲具有选择的第一频率范围以在电路结构附近产生多个塌陷气泡。 塌陷气泡产生第二多个声波脉冲，其具有靠近或包括电路结构的固有频率的第二频率范围，由此第二多个声波脉冲导致电路结构谐振。 此后，检查电路结构是否有结构损坏。 有利于早期鉴定晶体缺陷。

公开(公告)号：US06352867B1

公开(公告)日：2002-03-05

申请号：US09478181

申请日：2000-01-05

申请人： Terri A. Couteau ,  William Jarrett Campbell ,  Anthony J. Toprac

发明人： Terri A. Couteau ,  William Jarrett Campbell ,  Anthony J. Toprac

IPC分类号： H01L2100

CPC分类号： H01L21/32134

摘要： The present invention is directed to a method of controlling the width of a gate electrode based upon the etch rate of a chemical bath. In one illustrative embodiment, the method comprises determining an etching rate for a chemical bath, determining the manufactured width of the gate electrode, and varying the time duration of an etching process performed in the bath depending upon the etch rate of the bath and the width of the gate electrode.

摘要翻译： 本发明涉及一种基于化学浴蚀刻速率来控制栅电极的宽度的方法。 在一个说明性实施例中，该方法包括确定用于化学浴的蚀刻速率，确定制造的栅电极的宽度，并且根据镀液的蚀刻速率和宽度来改变在镀液中进行的蚀刻工艺的持续时间 的栅电极。