公开(公告)号：US5376848A

公开(公告)日：1994-12-27

申请号：US43112

申请日：1993-04-05

申请人： C. Christopher Hanke, III ,  William F. Johnstone ,  Michael W. Hodel ,  Tzu-Hui P. Hu ,  Barry Heim

发明人： C. Christopher Hanke, III ,  William F. Johnstone ,  Michael W. Hodel ,  Tzu-Hui P. Hu ,  Barry Heim

IPC分类号： H03H11/26 ,  H03K3/356 ,  H03K3/3562 ,  H03K5/00 ,  H03K5/13 ,  H03K5/135 ,  H03L7/081 ,  H03L7/18 ,  H03K3/366

CPC分类号： H03K5/133 ,  H03K3/35625 ,  H03L7/18 ,  H03K2005/00117

摘要： A delay matching circuit has a first node (48), a second node (50), a first loading circuit (54, 56), a second loading circuit (58, 60), a third loading circuit (64) and a buffer circuit (62). The first loading circuit couples a first logic state to the first node responsive to a first state of a control signal. The second loading circuit couples a second logic state to the first node responsive to a second state of the control signal. The buffer circuit electrically couples the first and second nodes. The first loading circuit, second loading circuit and buffer circuit are characterized by a first, a second and a third predetermined electrical impedance, respectively. The third loading circuit is coupled to the second node and is characterized by a fourth predetermined electrical impedance. The disclosed delay matching circuit propagates a clock signal input with a delay equal to the Clock-to-Q delay associated with a flip-flop constructed with similar circuit elements. The disclosed delay matching circuit is useful in circuits, such as phase locked loops, where the simultaneous propagation of two signals is critical.

摘要翻译： 延迟匹配电路具有第一节点（48），第二节点（50），第一加载电路（54,56），第二加载电路（58,60），第三加载电路（64）和缓冲电路 （62）。 响应于控制信号的第一状态，第一加载电路将第一逻辑状态耦合到第一节点。 响应于控制信号的第二状态，第二加载电路将第二逻辑状态耦合到第一节点。 缓冲电路电耦合第一和第二节点。 第一负载电路，第二负载电路和缓冲电路的特征在于分别具有第一，第二和第三预定电阻抗。 第三加载电路耦合到第二节点并且其特征在于第四预定电阻抗。 所公开的延迟匹配电路传播具有等于与由类似电路元件构造的触发器相关联的时钟到Q延迟的延迟的时钟信号输入。 所公开的延迟匹配电路在诸如锁相环路的电路中是有用的，其中两个信号的同时传播是关键的。

公开(公告)号：US5304953A

公开(公告)日：1994-04-19

申请号：US80012

申请日：1993-06-01

申请人： Barry B. Heim ,  Michael W. Hodel ,  Paul T. Hu

发明人： Barry B. Heim ,  Michael W. Hodel ,  Paul T. Hu

IPC分类号： H03L7/095 ,  H03L7/10

CPC分类号： H03L7/095 ,  H03L7/10 ,  Y10S331/02

摘要： A circuit (10) for providing recovery of a phase locked loop circuit when lock has been lost has been provided. The circuit includes a lock indicator circuit (24) for detecting when the phase locked loop circuit has lost lock on an input reference signal. When such loss has occurred, an override circuit (28) is rendered operative to decrease the voltage appearing at the input of a VCO within the phase locked loop thereby slowing down the frequency of the VCO and allowing the phase locked loop circuit to recover lock. Further, a logic circuit (30) detects when the voltage appearing at the input of the VCO has fallen below a predetermined threshold voltage and renders the override circuit non-operative.

摘要翻译： 已经提供了一种用于在锁定已经丢失时提供锁相环电路的恢复的电路（10）。 该电路包括锁定指示器电路（24），用于检测锁相环电路何时已经失去对输入参考信号的锁定。 当发生这种损耗时，可以使超控电路（28）工作，以降低出现在锁相环内的VCO输入处的电压，从而减慢VCO的频率，并允许锁相环电路恢复锁定。 此外，逻辑电路（30）检测出现在VCO的输入处的电压何时已经降到预定阈值电压以下，并且使超控电路不起作用。

公开(公告)号：US6166766A

公开(公告)日：2000-12-26

申请号：US929125

申请日：1997-09-03

申请人： Kendall G. Moore ,  Frederic B. Shapiro ,  Deborah J. Beckwith ,  Michael W. Hodel

发明人： Kendall G. Moore ,  Frederic B. Shapiro ,  Deborah J. Beckwith ,  Michael W. Hodel

IPC分类号： G06T1/00 ,  H04N5/217

CPC分类号： H04N5/3575 ,  H04N5/3658 ,  H04N5/378

摘要： A sensing circuit (202) uses correlated double sampling to sample a first pixel signal of a pixel stream (V.sub.PIXEL) at two different times to produce a dark signal and a light signal on two capacitors (310, 314). The dark and light signals are amplified in an amplifier (302) to produce a differential output signal (V.sub.PP -V.sub.PN) proportional to their difference. While the samples of the first pixel signal are being amplified, a second pixel signal is double-sampled to produce dark and light signals on two other capacitors (312, 316) for amplifying in the same amplifier. The period of the pixel signal is divided into time slots (T.sub.1 -T.sub.16) by a clocked oscillator (52). Programming signals (PROG1, PROG2) control the time slots in which sampling control pulses (V.sub.S1, V.sub.S2) are generated.

摘要翻译： 感测电路（202）使用相关双采样在两个不同时间对像素流（VPIXEL）的第一像素信号进行采样，以在两个电容器（310,314）上产生暗信号和光信号。 暗信号和光信号在放大器（302）中被放大，以产生与它们的差成比例的差分输出信号（VPP-VPN）。 当第一像素信号的样本被放大时，第二像素信号被双采样以在另外两个电容器（312,316）上产生暗和光信号，以在同一放大器中进行放大。 像素信号的周期由时钟振荡器（52）分为时隙（T1-T16）。 编程信号（PROG1，PROG2）控制产生采样控制脉冲（VS1，VS2）的时隙。

公开(公告)号：US5359297A

公开(公告)日：1994-10-25

申请号：US141361

申请日：1993-10-28

申请人： Michael W. Hodel ,  William H. Gulliver

发明人： Michael W. Hodel ,  William H. Gulliver

IPC分类号： H03L3/00 ,  H03L7/089 ,  H03L7/10 ,  H03L7/093

CPC分类号： H03L3/00 ,  H03L7/0891 ,  H03L7/10

摘要： A power-on reset circuit controls a PLL to prevent overshoot of the VCO during power-up. The power-on reset circuit asserts a control signal upon detecting the power supply potential to the PLL below a predetermined threshold. The control signal enables a pull-down transistor to attenuate the control voltage to the VCO and reduce the output frequency of the VCO. The control signal further blocks the input reference signal to the phase detector. With the input reference signal blocked, the phase detector produces only down pulses to the charge pump during subsequent high to low logic transitions of the feedback signal from the VCO thereby further discharging the loop node and reducing the output frequency of the VCO. Following power-up, the control signal disables the pull-down transistor and allows the input reference signal to reach the phase detector whereby the PLL begins normal frequency acquisition and lock sequencing.

摘要翻译： 上电复位电路控制PLL以防止在上电期间VCO的过冲。 当检测到PLL的电源电位低于预定阈值时，上电复位电路断言控制信号。 控制信号使得下拉晶体管能够衰减到VCO的控制电压并降低VCO的输出频率。 控制信号进一步阻止到相位检测器的输入参考信号。 当输入参考信号被阻塞时，相位检测器在来自VCO的反馈信号的随后的高到低逻辑转换期间仅向电荷泵产生下降脉冲，从而进一步放电环路节点并降低VCO的输出频率。 上电后，控制信号禁止下拉晶体管，并允许输入参考信号到达相位检测器，从而PLL开始正常的频率采集和锁定排序。