公开(公告)号：US07218161B2

公开(公告)日：2007-05-15

申请号：US10922798

申请日：2004-08-20

申请人： Chung Kuang Chen

发明人： Chung Kuang Chen

IPC分类号： H03H11/26

CPC分类号： G11C7/22 ,  G11C7/04 ,  G11C7/222 ,  H03K2005/00097 ,  H03K2005/00117 ,  H03K2005/00143

摘要： Methods and apparatuses are discussed for generating a temperature compensated signal, used for example to provide a signal with a delay within a pre-specified range over a range of temperatures to a sense amplifier of a memory array. In response to a start signal, a varying signal is generated. A clock signal causes additional loads of impedance to be coupled to the varying signal, for example via control circuitry generating temperature compensating signals.

摘要翻译： 讨论了用于产生温度补偿信号的方法和装置，其用于例如在存储器阵列的读出放大器的温度范围内提供具有在预定范围内的预定范围内的延迟的信号。 响应于启动信号，产生变化的信号。 时钟信号使额外的阻抗负载耦合到变化信号，例如通过产生温度补偿信号的控制电路。

公开(公告)号：US07692459B2

公开(公告)日：2010-04-06

申请号：US11878411

申请日：2007-07-24

申请人： Chao-Cheng Lee

发明人： Chao-Cheng Lee

IPC分类号： H03H9/38 ,  H03M1/12

CPC分类号： H03K5/131 ,  H03K2005/00117 ,  H03K2005/00123 ,  H03K2005/0013 ,  H03K2005/00143

摘要： A delay adjustor for adjusting the delay time of a signal, the adjustor comprising: a first capacitance unit and a variable capacitance unit serially coupled to the first capacitor wherein the capacitance of the variable capacitance unit is adjusted according to a first control signal and the variable capacitance unit comprises a plurality of second capacitors and at least a first switch coupled to the at least one capacitor of the second capacitors.

摘要翻译： 一种用于调整信号的延迟时间的延迟调整器，所述调整器包括：第一电容单元和串联耦合到所述第一电容器的可变电容单元，其中根据第一控制信号调整所述可变电容单元的电容， 电容单元包括多个第二电容器和耦合到第二电容器的至少一个电容器的至少第一开关。

公开(公告)号：US20060038600A1

公开(公告)日：2006-02-23

申请号：US10922798

申请日：2004-08-20

申请人： Chung Chen

发明人： Chung Chen

IPC分类号： H03H11/26

CPC分类号： G11C7/22 ,  G11C7/04 ,  G11C7/222 ,  H03K2005/00097 ,  H03K2005/00117 ,  H03K2005/00143

摘要： Methods and apparatuses are discussed for generating a temperature compensated signal, used for example to provide a signal with a delay within a pre-specified range over a range of temperatures to a sense amplifier of a memory array. In response to a start signal, a varying signal is generated. A clock signal causes additional loads of impedance to be coupled to the varying signal, for example via control circuitry generating temperature compensating signals.

摘要翻译： 讨论了用于产生温度补偿信号的方法和装置，其用于例如在存储器阵列的读出放大器的温度范围内提供具有在预定范围内的预定范围内的延迟的信号。 响应于启动信号，产生变化的信号。 时钟信号使额外的阻抗负载耦合到变化信号，例如通过产生温度补偿信号的控制电路。

公开(公告)号：US5376848A

公开(公告)日：1994-12-27

申请号：US43112

申请日：1993-04-05

申请人： C. Christopher Hanke, III ,  William F. Johnstone ,  Michael W. Hodel ,  Tzu-Hui P. Hu ,  Barry Heim

发明人： C. Christopher Hanke, III ,  William F. Johnstone ,  Michael W. Hodel ,  Tzu-Hui P. Hu ,  Barry Heim

IPC分类号： H03H11/26 ,  H03K3/356 ,  H03K3/3562 ,  H03K5/00 ,  H03K5/13 ,  H03K5/135 ,  H03L7/081 ,  H03L7/18 ,  H03K3/366

CPC分类号： H03K5/133 ,  H03K3/35625 ,  H03L7/18 ,  H03K2005/00117

摘要： A delay matching circuit has a first node (48), a second node (50), a first loading circuit (54, 56), a second loading circuit (58, 60), a third loading circuit (64) and a buffer circuit (62). The first loading circuit couples a first logic state to the first node responsive to a first state of a control signal. The second loading circuit couples a second logic state to the first node responsive to a second state of the control signal. The buffer circuit electrically couples the first and second nodes. The first loading circuit, second loading circuit and buffer circuit are characterized by a first, a second and a third predetermined electrical impedance, respectively. The third loading circuit is coupled to the second node and is characterized by a fourth predetermined electrical impedance. The disclosed delay matching circuit propagates a clock signal input with a delay equal to the Clock-to-Q delay associated with a flip-flop constructed with similar circuit elements. The disclosed delay matching circuit is useful in circuits, such as phase locked loops, where the simultaneous propagation of two signals is critical.

摘要翻译： 延迟匹配电路具有第一节点（48），第二节点（50），第一加载电路（54,56），第二加载电路（58,60），第三加载电路（64）和缓冲电路 （62）。 响应于控制信号的第一状态，第一加载电路将第一逻辑状态耦合到第一节点。 响应于控制信号的第二状态，第二加载电路将第二逻辑状态耦合到第一节点。 缓冲电路电耦合第一和第二节点。 第一负载电路，第二负载电路和缓冲电路的特征在于分别具有第一，第二和第三预定电阻抗。 第三加载电路耦合到第二节点并且其特征在于第四预定电阻抗。 所公开的延迟匹配电路传播具有等于与由类似电路元件构造的触发器相关联的时钟到Q延迟的延迟的时钟信号输入。 所公开的延迟匹配电路在诸如锁相环路的电路中是有用的，其中两个信号的同时传播是关键的。

公开(公告)号：US20080048748A1

公开(公告)日：2008-02-28

申请号：US11878411

申请日：2007-07-24

申请人： Chao-Cheng Lee

发明人： Chao-Cheng Lee

IPC分类号： H03H11/26

CPC分类号： H03K5/131 ,  H03K2005/00117 ,  H03K2005/00123 ,  H03K2005/0013 ,  H03K2005/00143

摘要： A delay adjustor for adjusting the delay time of a signal, the adjustor comprising: a first capacitance unit and a variable capacitance unit serially coupled to the first capacitor wherein the capacitance of the variable capacitance unit is adjusted according to a first control signal and the variable capacitance unit comprises a plurality of second capacitors and at least a first switch coupled to the at least one capacitor of the second capacitors.

摘要翻译： 一种用于调整信号的延迟时间的延迟调整器，所述调整器包括：第一电容单元和串联耦合到所述第一电容器的可变电容单元，其中根据第一控制信号调整所述可变电容单元的电容， 电容单元包括多个第二电容器和耦合到第二电容器的至少一个电容器的至少第一开关。

公开(公告)号：US6166576A

公开(公告)日：2000-12-26

申请号：US145744

申请日：1998-09-02

申请人： Eric J. Stave

发明人： Eric J. Stave

IPC分类号： G11C7/10 ,  G11C11/417 ,  H03K5/00 ,  H03K5/13 ,  H03K19/00 ,  H03H11/26

CPC分类号： G11C7/222 ,  G11C7/1072 ,  G11C11/417 ,  H03K5/131 ,  H03K19/0005 ,  H03K2005/00117 ,  H03K2005/00123

摘要： The present invention provides a method for controlling a timing of a digital component having an impedance-input terminal. The method includes determining an impedance level present at the impedance-input terminal, and delaying the timing of the digital component based on the impedance level. The present invention also provides a digital component and a system, where the digital component includes an impedance-input terminal and an impedance matching circuit that is capable of determining an impedance level present at the impedance-input terminal. The digital component also includes a delay circuit that is capable of delaying a timing of the digital component based on the impedance level.

摘要翻译： 本发明提供了一种用于控制具有阻抗输入端子的数字部件的定时的方法。 该方法包括确定存在于阻抗输入端的阻抗水平，以及基于阻抗水平延迟数字分量的定时。 本发明还提供一种数字部件和系统，其中数字部件包括能够确定阻抗输入端子处存在的阻抗电平的阻抗输入端子和阻抗匹配电路。 数字分量还包括能够基于阻抗水平延迟数字分量的定时的延迟电路。

公开(公告)号：US5095233A

公开(公告)日：1992-03-10

申请号：US655490

申请日：1991-02-14

申请人： Laurin Ashby ,  Paul E. Fletcher

发明人： Laurin Ashby ,  Paul E. Fletcher

IPC分类号： H03K5/00 ,  H03K5/13

CPC分类号： H03K5/133 ,  H03K2005/00117 ,  H03K2005/00195 ,  H03K2005/00247 ,  Y10S331/02

摘要： A phase lock loop for use in gate array applications with fixed transistors geometries maintains a predetermined phase delay between an input signal and an output signal. The phase comparison cycle operates over multiple periods of the input signal for increasing the operating frequency and simplifying timing considerations throughout the phase lock loop. A phase detector circuit detects a predetermined phase difference between the input signal and the output signal and provides a control signal and a clock signal at different transitions of the input signal. An up/down counter provides a count value migrating within a range of values in response to the control signal at the occurrence of the clock signal. The counter value selects a tap point of a delay line having single inverter resolution for delaying the input signal and maintaining the predetermined phase relationship between the input signal and the output signal of the phase lock loop. The updates to the delay line achieve steady state by waiting one or more periods of the input signal before the next phase comparison cycle preventing over-correction. The phase correction portion of the cycle is inhibited when the input signal and output signal are less than the predetermined phase difference thereby avoiding possible unnecessary corrections to the phase lock loop. The phase lock loop may be functionally divided amony multiple macros in a gate array library and conveniently disposed in the gate array.

摘要翻译： 用于具有固定晶体管几何形状的门阵列应用中的锁相环在输入信号和输出信号之间保持预定的相位延迟。 相位比较周期在输入信号的多个周期上运行，以增加工作频率，并简化整个锁相环的时序考虑。 相位检测器电路检测输入信号和输出信号之间的预定相位差，并在输入信号的不同转变处提供控制信号和时钟信号。 升/降计数器提供在时钟信号发生时响应于控制信号在值范围内迁移的计数值。 计数器值选择具有单个逆变器分辨率的延迟线的抽头点，用于延迟输入信号并保持输入信号和锁相环的输出信号之间的预定相位关系。 延迟线的更新通过在下一个相位比较周期之前等待输入信号的一个或多个周期来防止过度校正来实现稳定状态。 当输入信号和输出信号小于预定的相位差时，该周期的相位校正部分被禁止，从而避免了对锁相环的可能的不必要的校正。 锁相环可以在门阵列库中功能地分割多个宏，并且方便地设置在门阵列中。