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公开(公告)号：US5703821A
公开(公告)日：1997-12-30
申请号：US562736
申请日：1995-11-27
申请人： Andrea Baroni , Giovanni Mastrodomenico , Michele Taliercio , Piero Capocelli , Luigi Carro , Rajamohan Varambally
发明人： Andrea Baroni , Giovanni Mastrodomenico , Michele Taliercio , Piero Capocelli , Luigi Carro , Rajamohan Varambally
摘要： A single-port RAM generator architecture, for the generation of different RAM structures in a CAD environment, and to test the operation capabilities of the different RAM structure, The architecture includes a Static RAM matrix and a self timed architecture, which includes a control logic, both a dummy row and a dummy column having respectively equivalent load of a word line and of bit column of said matrix. The dummy column is discharged at a faster rate than the corresponding bit column optimizing the timing and reducing power consumption. Different column multiplexer selections provide different RAMs for a selected RAM size, each having slightly different silicon area and timing performance.
摘要翻译： 单端口RAM生成器架构，用于在CAD环境中生成不同的RAM结构，并测试不同RAM结构的操作能力。该架构包括一个静态RAM矩阵和一个自定时架构，其中包括一个控制逻辑 ，具有分别具有所述矩阵的字线和位列的等效负载的虚拟行和虚拟列。 虚拟列以比相应位列更快的速率放电，优化定时并降低功耗。 不同的列复用器选择为选定的RAM大小提供不同的RAM，每个RAM具有略微不同的硅面积和时序性能。
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2.发明授权公开(公告)号：US06598190B1
公开(公告)日：2003-07-22
申请号：US09175220
申请日：1998-10-19
IPC分类号： G11C2900
CPC分类号： G11C29/72
摘要： A memory device generator for generating memory devices in a CAD environment, the generator composed of a library file containing predefined basic circuit components; memory array generation algorithm interacting with the library file for generating a variable-size memory array representation having a variable number of memory elements, and at least one redundant memory element; memory element selection circuit generation algorithm interacting with the library file for generating a memory element selection circuit to be associated with the memory array for selecting at least one memory element according to memory device address inputs. The memory element selection circuit generation algorithm having a subroutine for generating a variable-size content-addressable memory representation having a plurality of content-addressable memory locations each one associated to a respective memory element or to a redundant memory element, each of the content-addressable memory locations suitable for storing one of a set of values of the memory device address inputs and for selecting the respective memory element or redundant memory element when the memory device address inputs take the one value.
摘要翻译： 一种用于在CAD环境中生成存储器件的存储器件发生器，所述发生器由包含预定义的基本电路部件的库文件组成; 存储器阵列生成算法与库文件交互以产生具有可变数量的存储器元件的可变大小的存储器阵列表示，以及至少一个冗余存储器元件; 存储器元件选择电路生成算法与库文件交互，用于产生与存储器阵列相关联的存储器元件选择电路，用于根据存储器设备地址输入选择至少一个存储器元件。 存储元件选择电路生成算法具有用于生成具有多个可内容寻址的存储器位置的可变大小内容可寻址存储器表示的子程序，每个内容寻址存储器位置各自与相应的存储器元件或冗余存储器元件相关联， 可寻址存储器位置适于存储存储器件地址输入的一组值中的一个，并且当存储器件地址输入采用一个值时用于选择相应的存储器元件或冗余存储器元件。
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公开(公告)号：US5471428A
公开(公告)日：1995-11-28
申请号：US159181
申请日：1993-11-30
申请人： Andrea Baroni , Giovanni Mastrodomenico , Taliercio Michele , Piero Capocelli , Luigi Carro , Rajamohan Varambally
发明人： Andrea Baroni , Giovanni Mastrodomenico , Taliercio Michele , Piero Capocelli , Luigi Carro , Rajamohan Varambally
摘要： A single-port RAM generator architecture, for the generation of different RAM structures in a CAD environment, and to test the operation capabilities of the different RAM structure. The architecture includes a Static RAM matrix and a self timed architecture, which includes a control logic, both a dummy row and a dummy column having respectively equivalent load of a word line and of bit column of said matrix. The dummy column is discharged at a faster rate than the corresponding bit column optimizing the timing and reducing power consumption. Different column multiplexer selections provide different RAMs for a selected RAM size, each having slightly different silicon area and timing performance.
摘要翻译： 单端口RAM生成器架构，用于在CAD环境中生成不同的RAM结构，并测试不同RAM结构的操作能力。 该架构包括静态RAM矩阵和自定时架构，其包括控制逻辑，虚拟行和虚拟列，分别具有字线和所述矩阵的位列的等效负载。 虚拟列以比相应位列更快的速率放电，优化定时并降低功耗。 不同的列复用器选择为选定的RAM大小提供不同的RAM，每个RAM具有略微不同的硅面积和时序性能。
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4.发明授权Analog integrated circuit having intrinsic topologies and characteristics selectable by a digital control 失效具有可由数字控制选择的固有拓扑和特性的模拟集成电路
公开(公告)号：US4875020A
公开(公告)日：1989-10-17
申请号：US287299
申请日：1988-12-21
CPC分类号： G06J1/00
摘要： An integrated analog circuit having a circuit topology and intrinsic characteristics which may be selected by digital control means is formed by batteries of similar circuit components arranged substantially in parallel or in a matrix array, anyone of which may be isolated or not by means of a dedicated integrated switch and by alternative interconnection paths among the different circuit components and/or batteries of circuit components, which may be also be selected by closing a relative integrated switch. A dedicated nonvolatile memory, integrated on the same chip may be permanently programmed and determine a certain configuration of all the integrated switches thus selected a particlar component or more components of each of said batteries of functionally similar components, and/or selecting a certain interconnection path among the different circuit components in order to form a functional integrated circuit having the desired topology and intrinsic characteristics. The integrated nonvolatile memory is programmed by means of a software program which may take as input data the desired values of the different parameters which determine the intrinsic characteristics of the functional analog circuit and the type of functional analog circuit itself.
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公开(公告)号：USRE42250E1
公开(公告)日：2011-03-29
申请号：US09927426
申请日：2001-08-10
IPC分类号： H03K5/13
摘要： A reduced area delay circuit and method are disclosed. The delay circuit uses a constant current source and a constant current drain to charge and discharge a capacitor and thus control the delay time of the delay circuit. The constant current source and drain can be implemented using current mirrors formed by configuring MOSFET transistors in a common source configuration. The delay circuit method includes the steps of receiving an input signal, delaying the input signal by using a constant current source or drain in combination with a capacitor, and then buffering the voltage on the capacitor using two inverters. A programmable delay circuit is also disclosed by adding additional pairs of current mirrors to the delay circuit and selectively enabling the pairs to adjust the delay time.
摘要翻译： 公开了一种缩小面积延迟电路和方法。 延迟电路使用恒流源和恒流漏极来对电容器进行充电和放电，从而控制延迟电路的延迟时间。 恒流源和漏极可以使用通过在共同的源配置中配置MOSFET晶体管形成的电流镜来实现。 延迟电路方法包括以下步骤：接收输入信号，通过使用恒定电流源或漏极与电容器组合来延迟输入信号，然后使用两个反相器缓冲电容器上的电压。 还公开了可编程延迟电路，通过向延迟电路增加额外的电流镜对，并且选择性地使得对可以调整延迟时间。
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公开(公告)号：US5936451A
公开(公告)日：1999-08-10
申请号：US897187
申请日：1997-07-21
摘要： A reduced area delay circuit and method are disclosed. The delay circuit uses a constant current source and a constant current drain to charge and discharge a capacitor and thus control the delay time of the delay circuit. The constant current source and drain can be implemented using current mirrors formed by configuring MOSFET transistors in a common source configuration. The delay circuit method includes the steps of receiving an input signal, delaying the input signal by using a constant current source or drain in combination with a capacitor, and then buffering the voltage on the capacitor using two inverters. A programmable delay circuit is also disclosed by adding additional pairs of current mirrors to the delay circuit and selectively enabling the pairs to adjust the delay time.
摘要翻译： 公开了一种缩小面积延迟电路和方法。 延迟电路使用恒流源和恒流漏极来对电容器进行充电和放电，从而控制延迟电路的延迟时间。 恒流源和漏极可以使用通过在共同的源配置中配置MOSFET晶体管形成的电流镜来实现。 延迟电路方法包括以下步骤：接收输入信号，通过使用恒定电流源或漏极与电容器组合来延迟输入信号，然后使用两个反相器缓冲电容器上的电压。 还公开了可编程延迟电路，通过向延迟电路增加额外的电流镜对，并且选择性地使得对可以调整延迟时间。
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公开(公告)号：US5936298A
公开(公告)日：1999-08-10
申请号：US761185
申请日：1996-12-06
申请人： Piero Capocelli , Raffaele Zambrano , Federico Pio , Carlo Riva
发明人： Piero Capocelli , Raffaele Zambrano , Federico Pio , Carlo Riva
IPC分类号： H01F17/00 , H01F41/04 , H01L23/522 , H01L29/00
CPC分类号： H01F41/046 , H01F17/0033 , H01L23/5227 , H01F2017/0086 , H01L2924/0002
摘要： Inductive structures make highly efficient use of the magnetic flux generd, and are consistent with integrated circuit manufacturing techniques. The structures include electrically conductive layers and interconnecting conductor filled vias to define a helical winding surrounding a closed magnetic core. The magnetic core may also be formed by semiconductor manufacturing techinuqes. A method of making the structures on a semiconductor substrate concurrently with the formation of the integrated circuit itself is also disclosed.
摘要翻译： 感应结构高效地利用所产生的磁通量，并与集成电路制造技术保持一致。 这些结构包括导电层和互连导体填充的通孔，以限定围绕封闭磁芯的螺旋绕组。 磁芯也可以由半导体制造技术形成。 还公开了与形成集成电路本身同时在半导体衬底上制造结构的方法。
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