摘要:
A method of the present invention includes the steps of forming an amorphous semiconductor layer on an insulative surface, adding a catalyst element capable of promoting crystallization to the amorphous semiconductor layer and then performing a first heat treatment so as to crystallize the amorphous semiconductor layer, thereby obtaining a crystalline semiconductor layer, performing a first gettering process to remove the catalyst element from the semiconductor layer, and performing a second gettering process that is different from the first gettering process to remove the catalyst element from the semiconductor layer. The first gettering process includes removing at least large masses of a semiconductor compound of the catalyst element present in the crystalline semiconductor layer. The second gettering process includes moving at least a portion of the catalyst element remaining in the crystalline semiconductor layer so as to form a low-catalyst-concentration region in the crystalline semiconductor layer, the low-catalyst-concentration region having a lower catalyst element concentration than in other regions.
摘要:
A base film is formed for the TFTs in order to prevent diffusion of impurities from the glass substrate into the active layer, to maintain stability in the characteristics such as Vth and S-value of the TFTs and to maintain enhanced productivity. A film in which the composition ratios of N, O and H are continuously changed by changing the flow rates of H2 and N2O, is used as the base film to prevent a change in the TFT characteristics. The base film can be formed by varying the flow rates of H2 and N2O in the same film-forming chamber to enhance the productivity.
摘要:
A crystalline semiconductor film, the crystalline semiconductor film being formed over an insulative substrate, and including semiconductor crystal grains laterally grown along a surface of the insulative substrate, wherein the laterally-grown semiconductor crystal grains are in contact with each other at grain boundaries, and a distance between adjacent grain boundaries is equal to or smaller than two times a lateral growth distance of the semiconductor crystal grains.